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| author | Greg Watson <jarrah@users.sourceforge.net> | 2003-06-13 22:07:53 +0000 |
|---|---|---|
| committer | Greg Watson <jarrah@users.sourceforge.net> | 2003-06-13 22:07:53 +0000 |
| commit | f7092040fd4aba081aad75116c2b9594149d5c66 (patch) | |
| tree | 9fff13449dd1e397292668313b57537ade1739d8 /src/southbridge | |
| parent | 26ba0f5f9bb04e296c3a6320a855639c2f14e83c (diff) | |
| download | coreboot-f7092040fd4aba081aad75116c2b9594149d5c66.tar.xz | |
More FB2 stuff
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@877 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/winbond/w83c553/w83c553f.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/southbridge/winbond/w83c553/w83c553f.c b/src/southbridge/winbond/w83c553/w83c553f.c index daca1c11bb..2d9daaea93 100644 --- a/src/southbridge/winbond/w83c553/w83c553f.c +++ b/src/southbridge/winbond/w83c553/w83c553f.c @@ -27,7 +27,6 @@ * Enabling function 1 (IDE controller of the chip. */ -#include <types.h> #include <arch/io.h> #include <device/pci.h> #include <console/console.h> @@ -47,7 +46,7 @@ #define CONFIG_IDE_MAXDEVICE (CONFIG_IDE_MAXBUS*2) #endif -u32 ide_bus_offset[CONFIG_IDE_MAXBUS]; +uint32_t ide_bus_offset[CONFIG_IDE_MAXBUS]; void initialise_pic(void); void initialise_dma(void); |