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authorVladimir Serbinenko <phcoder@gmail.com>2014-08-31 00:27:05 +0200
committerVladimir Serbinenko <phcoder@gmail.com>2014-10-15 10:54:36 +0200
commit0e64617d7d8adcd4d3db16eed7a34604691c2ee6 (patch)
tree8ab26fb0563a61ca3a8f1d3ced7d455aca845583 /src/southbridge
parent33769a5caadca0ff82267ab5021bc85315e1d7f5 (diff)
downloadcoreboot-0e64617d7d8adcd4d3db16eed7a34604691c2ee6.tar.xz
i945: Convert to per-device ACPI
Change-Id: Iee3ee33ca58b8c722d2d38aae31e7130032512ad Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6804 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/i82801gx/acpi/globalnvs.asl4
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c24
-rw-r--r--src/southbridge/intel/i82801gx/nvs.h2
3 files changed, 28 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
index 0384376417..027391c75d 100644
--- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
@@ -30,8 +30,8 @@ Name(\DSEN, 1) // Display Output Switching Enable
* we have to fix it up in coreboot's ACPI creation phase.
*/
-
-OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x100)
+External(NVSA)
+OperationRegion (GNVS, SystemMemory, NVSA, 0x100)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index b20833990a..279bea61e4 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -31,6 +31,10 @@
#include <cpu/cpu.h>
#include "i82801gx.h"
#include <cpu/x86/smm.h>
+#include <arch/acpigen.h>
+#include <cbmem.h>
+#include <string.h>
+#include "nvs.h"
#define NMI_OFF 0
@@ -488,6 +492,24 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
+static void southbridge_inject_dsdt(void)
+{
+ global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
+
+ if (gnvs) {
+ int scopelen;
+ memset(gnvs, 0, sizeof(*gnvs));
+ acpi_create_gnvs(gnvs);
+ /* And tell SMI about it */
+ smm_setup_structures(gnvs, NULL, NULL);
+
+ /* Add it to SSDT. */
+ scopelen = acpigen_write_scope("\\");
+ scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs);
+ acpigen_patch_len(scopelen - 1);
+ }
+}
+
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
};
@@ -496,6 +518,8 @@ static struct device_operations device_ops = {
.read_resources = i82801gx_lpc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
+ .acpi_inject_dsdt_generator = southbridge_inject_dsdt,
+ .write_acpi_tables = acpi_write_hpet,
.init = lpc_init,
.scan_bus = scan_static_bus,
.enable = i82801gx_enable,
diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h
index 14f0ad36c1..cf4065c63f 100644
--- a/src/southbridge/intel/i82801gx/nvs.h
+++ b/src/southbridge/intel/i82801gx/nvs.h
@@ -135,3 +135,5 @@ typedef struct {
u8 bten;
u8 rsvd13[14];
} __attribute__((packed)) global_nvs_t;
+
+void acpi_create_gnvs(global_nvs_t *gnvs);