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authorTim Chen <tim-chen@quanta.corp-partner.google.com>2020-07-15 20:19:10 +0800
committerEdward O'Callaghan <quasisec@chromium.org>2020-07-20 12:37:19 +0000
commit24a61841e312773d6be2be6bca955fff9272ed81 (patch)
tree7711d08f6ced834d2625025c51bbd9b6acc1d876 /src/southbridge
parent3658c629086754fd4ad66d64f7d9862acfe31ef5 (diff)
downloadcoreboot-24a61841e312773d6be2be6bca955fff9272ed81.tar.xz
mb/google/puff: update USB3 gen2 parameters
Based on USB3 gen2 SI report to fine tune the parameters for USB3 gen2. BRANCH=none BUG=b:150515720 TEST=build and check the USB3 gen2 register on DUT is correct. Change-Id: I6ec109871d682a1ae2fa4c22fdd6b87ad8a39e9e Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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