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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-08-12 09:50:48 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-18 12:14:47 +0000 |
| commit | 27ce8e3296fb6a55c286b7ff84a03102e41d7a3a (patch) | |
| tree | 6b09bc489d7eb6d6ae37f093d5a2d163e1c981e2 /src/southbridge | |
| parent | eaa165dfb4221b92f3934fcdf7247f9e386fe353 (diff) | |
| download | coreboot-27ce8e3296fb6a55c286b7ff84a03102e41d7a3a.tar.xz | |
sb/intel/lynxpoint/early_pch.c: Use common 'write_pmbase16()'
Change-Id: I1a70eea8c4f835e5673e75282c9cecb24b150e3d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_pch.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index e74fdc5849..85f9f33a97 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -6,6 +6,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/smbus_host.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmclib.h> #include <elog.h> #include "pch.h" @@ -57,7 +58,7 @@ static void pch_generic_setup(void) { printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + write_pmbase16(0x60 | 0x08, (1 << 11)); /* halt timer */ printk(BIOS_DEBUG, " done.\n"); } |