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authorStefan Reinauer <stepan@coresystems.de>2010-04-20 11:03:41 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-20 11:03:41 +0000
commit29ceae2c370fcd5a7c159771050611f03de006ba (patch)
tree67cbf65425fc9147842d3b2c4fb634bd2c0b5efe /src/southbridge
parentea6772d306fc38fc934792cade14f0c8fc0a4ae5 (diff)
downloadcoreboot-29ceae2c370fcd5a7c159771050611f03de006ba.tar.xz
As Myles suggested a while back: Switch long time #warnings to be comments
only. Keeping them as #warnings will not likely that they're fixed. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/sb600/sb600_early_setup.c2
-rw-r--r--src/southbridge/amd/sb700/sb700_early_setup.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/sb600/sb600_early_setup.c b/src/southbridge/amd/sb600/sb600_early_setup.c
index 274eda002f..1ba9e5180c 100644
--- a/src/southbridge/amd/sb600/sb600_early_setup.c
+++ b/src/southbridge/amd/sb600/sb600_early_setup.c
@@ -88,7 +88,7 @@ static void sb600_lpc_init(void)
dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0); /* LPC Controller */
/* Decode port 0x3f8-0x3ff (Serial 0) */
-#warning Serial port decode on LPC is hardcoded to 0x3f8
+ // XXX Serial port decode on LPC is hardcoded to 0x3f8
reg8 = pci_read_config8(dev, 0x44);
reg8 |= 1 << 6;
pci_write_config8(dev, 0x44, reg8);
diff --git a/src/southbridge/amd/sb700/sb700_early_setup.c b/src/southbridge/amd/sb700/sb700_early_setup.c
index 8aca04d9a0..4315c39545 100644
--- a/src/southbridge/amd/sb700/sb700_early_setup.c
+++ b/src/southbridge/amd/sb700/sb700_early_setup.c
@@ -119,7 +119,7 @@ static void sb700_lpc_init(void)
dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
/* Decode port 0x3f8-0x3ff (Serial 0) */
-#warning Serial port decode on LPC is hardcoded to 0x3f8
+ // XXX Serial port decode on LPC is hardcoded to 0x3f8
reg8 = pci_read_config8(dev, 0x44);
reg8 |= 1 << 6;
pci_write_config8(dev, 0x44, reg8);