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authorDave Frodin <dave.frodin@se-eng.com>2012-02-02 14:56:23 -0700
committerMarc Jones <marcj303@gmail.com>2012-02-20 18:58:07 +0100
commit2eacc0eec23fbe3a68eb17e32b2603d4c3353a36 (patch)
tree843652c6dfbce618113ad2c6a74b4293879a7fb0 /src/southbridge
parentd8d8c63cf71efbc8fae21e3db8aea87b530111f9 (diff)
downloadcoreboot-2eacc0eec23fbe3a68eb17e32b2603d4c3353a36.tar.xz
Force SB800 bootblock to use I/O for PCI config
If PCI config cycles use MMIO instead of I/O in the bootblock code the cycles will go nowhere since the MMIO feature hasn't been configured yet. This change forces the cycles to use I/O. Change-Id: I93dec45f7cd6764cef7736c774a4d4e61bf7d7e0 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/630 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/sb800/bootblock.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c
index 18eae24312..30d6ac6737 100644
--- a/src/southbridge/amd/sb800/bootblock.c
+++ b/src/southbridge/amd/sb800/bootblock.c
@@ -39,15 +39,15 @@ static void sb800_enable_rom(void)
dev = PCI_DEV(0, 0x14, 3);
/* Decode variable LPC ROM address ranges 1 and 2. */
- reg8 = pci_read_config8(dev, 0x48);
+ reg8 = pci_io_read_config8(dev, 0x48);
reg8 |= (1 << 3) | (1 << 4);
- pci_write_config8(dev, 0x48, reg8);
+ pci_io_write_config8(dev, 0x48, reg8);
/* LPC ROM address range 1: */
/* Enable LPC ROM range mirroring start at 0x000e(0000). */
- pci_write_config16(dev, 0x68, 0x000e);
+ pci_io_write_config16(dev, 0x68, 0x000e);
/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
- pci_write_config16(dev, 0x6a, 0x000f);
+ pci_io_write_config16(dev, 0x6a, 0x000f);
/* LPC ROM address range 2: */
/*
@@ -57,9 +57,9 @@ static void sb800_enable_rom(void)
* 0xffe0(0000): 2MB
* 0xffc0(0000): 4MB
*/
- pci_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
+ pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
/* Enable LPC ROM range end at 0xffff(ffff). */
- pci_write_config16(dev, 0x6e, 0xffff);
+ pci_io_write_config16(dev, 0x6e, 0xffff);
}
static void bootblock_southbridge_init(void)