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authorVladimir Serbinenko <phcoder@gmail.com>2014-08-30 22:39:20 +0200
committerVladimir Serbinenko <phcoder@gmail.com>2014-10-15 10:54:27 +0200
commit33769a5caadca0ff82267ab5021bc85315e1d7f5 (patch)
tree5516792e4da43b83abbc327ce369be7ce9d01cd8 /src/southbridge
parent8ffc085e1affaabbe3dca8ac6a89346b71dfc02e (diff)
downloadcoreboot-33769a5caadca0ff82267ab5021bc85315e1d7f5.tar.xz
gm45: Convert to per-device ACPI
Change-Id: Ib04b03b2dc2ad3bfa886b43df9dd6518bbb46e3f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6803 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/i82801ix/Kconfig4
-rw-r--r--src/southbridge/intel/i82801ix/acpi/globalnvs.asl3
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c28
-rw-r--r--src/southbridge/intel/i82801ix/nvs.h2
4 files changed, 36 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index 92e7f41b8b..1ad5aad90a 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -34,6 +34,10 @@ config EHCI_BAR
hex
default 0xfef00000
+config HPET_MIN_TICKS
+ hex
+ default 0x80
+
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/i82801ix/bootblock.c"
diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
index 0384376417..d0505948ee 100644
--- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
@@ -31,7 +31,8 @@ Name(\DSEN, 1) // Display Output Switching Enable
*/
-OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x100)
+External(NVSA)
+OperationRegion (GNVS, SystemMemory, NVSA, 0x100)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index ea881119ff..8105a4dc16 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -31,7 +31,11 @@
#include <arch/acpi.h>
#include <cpu/cpu.h>
#include <cpu/x86/smm.h>
+#include <arch/acpigen.h>
+#include <cbmem.h>
+#include <string.h>
#include "i82801ix.h"
+#include "nvs.h"
#define NMI_OFF 0
@@ -534,6 +538,26 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
+#if IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES)
+static void southbridge_inject_dsdt(void)
+{
+ global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
+
+ if (gnvs) {
+ int scopelen;
+ memset(gnvs, 0, sizeof (*gnvs));
+ acpi_create_gnvs(gnvs);
+ /* And tell SMI about it */
+ smm_setup_structures(gnvs, NULL, NULL);
+
+ /* Add it to SSDT. */
+ scopelen = acpigen_write_scope("\\");
+ scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs);
+ acpigen_patch_len(scopelen - 1);
+ }
+}
+#endif
+
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
};
@@ -542,6 +566,10 @@ static struct device_operations device_ops = {
.read_resources = i82801ix_lpc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
+#if IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES)
+ .acpi_inject_dsdt_generator = southbridge_inject_dsdt,
+ .write_acpi_tables = acpi_write_hpet,
+#endif
.init = lpc_init,
.scan_bus = scan_static_bus,
.ops_pci = &pci_ops,
diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h
index 14f0ad36c1..cf4065c63f 100644
--- a/src/southbridge/intel/i82801ix/nvs.h
+++ b/src/southbridge/intel/i82801ix/nvs.h
@@ -135,3 +135,5 @@ typedef struct {
u8 bten;
u8 rsvd13[14];
} __attribute__((packed)) global_nvs_t;
+
+void acpi_create_gnvs(global_nvs_t *gnvs);