summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
authorRonald G. Minnich <rminnich@gmail.com>2006-04-27 15:10:55 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-04-27 15:10:55 +0000
commit3716427e7f63fd00e8117fca2027f2fe3a5bbf00 (patch)
tree6250710970f5c19492a76378c191d2590a496fcf /src/southbridge
parentb7a09b4f19aa5e9d23118d32e523470e590318eb (diff)
downloadcoreboot-3716427e7f63fd00e8117fca2027f2fe3a5bbf00.tar.xz
we don't need msr_init
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/cs5536/cs5536.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 37c54d5c50..ebe99cf395 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -29,11 +29,13 @@ static void southbridge_enable(struct device *dev)
msr.lo = sb->lpc_serirq_enable;
msr.hi = 0;
wrmsr(MDD_LPC_SIRQ, msr);
+ printk_debug("Enabled LPC SERIRQ 0x%x\n", msr.lo);
}
if (sb->lpc_irq) {
msr.lo = sb->lpc_irq;
msr.hi = 0;
wrmsr(MDD_IRQM_LPC, msr);
+ printk_debug("Enabled lpc irq values 0x%x\n", msr.lo);
}
if (sb->enable_gpio0_inta){
@@ -47,6 +49,7 @@ static void southbridge_enable(struct device *dev)
/* magic stuff */
outl(0x3081, GPIOL_INPUT_INVERT_ENABLE);
outl(GPIOL_0_SET, GPIO_MAPPER_X);
+ printk_debug("Enabled GPIO0 INTa\n");
}