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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-10-18 07:51:03 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-10-19 06:20:14 +0200
commit50c9637e15ddd78f896419f2335457de4fe22d77 (patch)
tree2a8b281211cce06473d47a5db76495a435064d72 /src/southbridge
parenta1ebbc42ad791369c2e4f626e46917bdb1459d72 (diff)
downloadcoreboot-50c9637e15ddd78f896419f2335457de4fe22d77.tar.xz
AGESA fam12 fam14 fam15: Sanitize BiosCallOuts headers
Change-Id: Ic08f1f2fdbcf6164eb1a0330f9134da3fdb978d7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7114 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/cimx/sb700/gpio_oem.h11
-rw-r--r--src/southbridge/amd/cimx/sb800/gpio_oem.h23
2 files changed, 34 insertions, 0 deletions
diff --git a/src/southbridge/amd/cimx/sb700/gpio_oem.h b/src/southbridge/amd/cimx/sb700/gpio_oem.h
new file mode 100644
index 0000000000..bc05e2a5b9
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/gpio_oem.h
@@ -0,0 +1,11 @@
+#ifndef _CIMX_SB_GPIO_OEM_H_
+#define _CIMX_SB_GPIO_OEM_H_
+
+#define SB_GPIO_REG01 1
+#define SB_GPIO_REG02 2
+#define SB_GPIO_REG15 15
+#define SB_GPIO_REG24 24
+#define SB_GPIO_REG25 25
+#define SB_GPIO_REG27 27
+
+#endif
diff --git a/src/southbridge/amd/cimx/sb800/gpio_oem.h b/src/southbridge/amd/cimx/sb800/gpio_oem.h
new file mode 100644
index 0000000000..a9f59e3a31
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb800/gpio_oem.h
@@ -0,0 +1,23 @@
+#ifndef _CIMX_SB_GPIO_OEM_H_
+#define _CIMX_SB_GPIO_OEM_H_
+
+#define SB_GPIO_REG02 2
+#define SB_GPIO_REG09 9
+#define SB_GPIO_REG10 10
+#define SB_GPIO_REG15 15
+#define SB_GPIO_REG17 17
+#define SB_GPIO_REG21 21
+#define SB_GPIO_REG25 25
+#define SB_GPIO_REG28 28
+
+/* FCH GPIO access helpers */
+#define FCH_IOMUX(gpio_nr) (*(u8*)(ACPI_MMIO_BASE+IOMUX_BASE+(gpio_nr)))
+#define FCH_PMIO(reg_nr) (*(u8*)(ACPI_MMIO_BASE+PMIO_BASE+(reg_nr)))
+#define FCH_GPIO(gpio_nr) (*(volatile u8*)(ACPI_MMIO_BASE+GPIO_BASE+(gpio_nr)))
+
+static inline u8 fch_gpio_state(unsigned int gpio_nr)
+{
+ return FCH_GPIO(gpio_nr) >> 7;
+}
+
+#endif