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| author | Keith Hui <buurin@gmail.com> | 2020-05-21 17:07:47 -0400 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-26 21:08:53 +0000 |
| commit | 55b1dbef3db0ac75ffb171d89def7b498801f5be (patch) | |
| tree | 93456626950e64d91ca245d0f5aae337c1c1c978 /src/southbridge | |
| parent | a5a8e0962a06ad57fbcebb2ec41a4442e392a898 (diff) | |
| download | coreboot-55b1dbef3db0ac75ffb171d89def7b498801f5be.tar.xz | |
sb/intel/i82371eb: Add #defines for DEVRESx registers
These will be put to use in a follow-up.
Change-Id: Id13dde5ce2239064b9b18de7ca516525158ae268
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 405bb74160..c6944ede9a 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -89,6 +89,16 @@ void i82371eb_early_init(void); #define PMBA 0x40 /* Power management base address */ #define DEFAULT_PMBASE 0xe400 #define PM_IO_BASE DEFAULT_PMBASE +#define DEVRESA 0X5c /* Device resource A */ +#define DEVRESB 0X60 /* Device resource B */ +#define DEVRESC 0X64 /* Device resource C */ +#define DEVRESD 0x52 /* Device resource D */ +#define DEVRESE 0x68 /* Device resource E */ +#define DEVRESF 0x6c /* Device resource F */ +#define DEVRESG 0x70 /* Device resource G */ +#define DEVRESH 0x74 /* Device resource H */ +#define DEVRESI 0x78 /* Device resource I */ +#define DEVRESJ 0x7c /* Device resource J */ #define PMREGMISC 0x80 /* Miscellaneous power management */ #define PMIOSE (1 << 0) /* PM I/O Space Enable */ |