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authorSindhoor Tilak <sindhoor@sin9yt.net>2020-07-19 12:36:47 +0000
committerPatrick Georgi <pgeorgi@google.com>2020-07-26 21:23:14 +0000
commit6217a15674eb73a3c453d8b1de40bc4e7ea3c90a (patch)
treeaf2d57cd2f977543271a12148e41fec326547e80 /src/southbridge
parentc25c1ebd9ed54d9c70d4c247c71fc19259751413 (diff)
downloadcoreboot-6217a15674eb73a3c453d8b1de40bc4e7ea3c90a.tar.xz
southbridge/intel/common: Replace outb with post_code in finalize.c
The outb() call is replaced with the post_code() The post_codes.h is replaced with console.h since console.h includes both the post_code definition and post_codes.h Change-Id: I21345260e86de30614c416e2f509bd77b9e00cb7 Signed-off-by: Sindhoor Tilak <sindhoor@sin9yt.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/common/finalize.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c
index 00c3a0ef87..59d429747c 100644
--- a/src/southbridge/intel/common/finalize.c
+++ b/src/southbridge/intel/common/finalize.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/io.h>
-#include <console/post_codes.h>
+#include <console/console.h>
#include <device/pci_ops.h>
#include <southbridge/intel/common/pmbase.h>
#include <southbridge/intel/common/pmutil.h>
@@ -48,5 +48,5 @@ void intel_pch_finalize_smm(void)
write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK);
- outb(POST_OS_BOOT, CONFIG_POST_IO_PORT);
+ post_code(POST_OS_BOOT);
}