ChangeLog:

Add initial ACPI support for M57SLI.
	Activates/Enables:
		* native Coreboot ACPI for M57SLI
		* Soft-Power-Off
		* PowerNow!
		* High Precision Event Timer
		* Windows booting with ACPI support

Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 179 insertions, 3 deletions

diff --git a/src/southbridge/nvidia/mcp55/Config.lb b/src/southbridge/nvidia/mcp55/Config.lb
index 1e44793fc4..f84fde780f 100644
--- a/src/southbridge/nvidia/mcp55/Config.lb
+++ b/src/southbridge/nvidia/mcp55/Config.lb
@@ -19,6 +19,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ## 
 
+uses HAVE_ACPI_TABLES
+
 config chip.h
 driver mcp55.o
 driver mcp55_usb.o
@@ -33,3 +35,6 @@ driver mcp55_pci.o
 driver mcp55_pcie.o
 driver mcp55_ht.o
 object mcp55_reset.o
+if HAVE_ACPI_TABLES
+	object mcp55_fadt.o
+end
diff --git a/src/southbridge/nvidia/mcp55/mcp55_fadt.c b/src/southbridge/nvidia/mcp55/mcp55_fadt.c
new file mode 100644
index 0000000000..66aba40252
--- /dev/null
+++ b/src/southbridge/nvidia/mcp55/mcp55_fadt.c
@@ -0,0 +1,173 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <nick.barker9@btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+
+extern unsigned pm_base;
+
+/* Create the Fixed ACPI Description Tables (FADT) for this board. */
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	device_t dev;
+	int is_mcp55 = 0;	
+	dev = dev_find_device(PCI_VENDOR_ID_NVIDIA,
+		PCI_DEVICE_ID_NVIDIA_MCP55_LPC, 0);
+	if (dev)
+		is_mcp55 = 1;
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 1;
+	memcpy(header->oem_id, "GBT", 6);
+	memcpy(header->oem_table_id, "COREBOOT ", 8);
+	memcpy(header->asl_compiler_id, "CORE", 4);
+	header->asl_compiler_revision = 42;
+
+	printk_info("ACPI: pm_base: %u...\n", pm_base);
+
+	fadt->firmware_ctrl = facs;
+	fadt->dsdt = dsdt;
+	fadt->preferred_pm_profile = 1; //check
+	fadt->sci_int = 9;
+	/* disable system management mode by setting to 0 */
+	fadt->smi_cmd = 0x0; //pm_base+0x42e; (value from proprietary acpi fadt) 
+	fadt->acpi_enable = 0xa1;
+	fadt->acpi_disable = 0xa0;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0x0;
+
+	fadt->pm1a_evt_blk = pm_base;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pm_base + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pm_base + 0x1c;
+	fadt->pm_tmr_blk = pm_base + 0x8;
+	fadt->gpe0_blk = pm_base + 0x20;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	if (is_mcp55) {
+		fadt->gpe1_blk = pm_base + 0x4a0;
+		fadt->gpe1_base = 0x20;
+		fadt->gpe1_blk_len = 0x10;
+	}
+	else {
+		fadt->gpe1_blk = 0x0;
+		fadt->gpe1_base = 0x0;
+		fadt->gpe1_blk_len = 0x0;
+	}
+
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = 0x65;
+	fadt->p_lvl3_lat = 0x3e9;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;	
+	fadt->day_alrm = 0x7d;
+	fadt->mon_alrm = 0x7e;
+	fadt->century = 0x32;
+
+	fadt->iapc_boot_arch = 0x0;
+
+	fadt->flags = 0x4a5;
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 0;
+	fadt->x_firmware_ctl_l = facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c
index 3cfcd57a71..4aff452958 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c
@@ -155,7 +155,6 @@ static void lpc_slave_init(device_t dev)
 	lpc_common_init(dev, 0);
 }
 
-#if 0
 static void enable_hpet(struct device *dev)
 {
 	unsigned long hpet_address;
@@ -164,7 +163,6 @@ static void enable_hpet(struct device *dev)
 	hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
 	printk_debug("enabling HPET @0x%x\n", hpet_address);
 }
-#endif
 
 static void lpc_init(device_t dev)
 {
@@ -242,7 +240,7 @@ static void lpc_init(device_t dev)
 	isa_dma_init();
 
 	/* Initialize the High Precision Event Timers */
-//	enable_hpet(dev);
+	enable_hpet(dev);
 
 }