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authorNico Huber <nico.huber@secunet.com>2015-10-01 19:00:51 +0200
committerNico Huber <nico.h@gmx.de>2015-10-16 22:47:22 +0000
commit7b2f9f6994341a890a11220a9d9fcbf7997bcae9 (patch)
tree62c6fd59dc3bda48969cb6499cfeb3348d71aadb /src/southbridge
parentf3214d02482a4104d7276f06d6b326b2a54c4262 (diff)
downloadcoreboot-7b2f9f6994341a890a11220a9d9fcbf7997bcae9.tar.xz
intel/southbridge/bd82x6x: Add option to set SPI VSCC registers
These are needed for the hardware-sequencing function of the PCH SPI interface. Values are specific to the flash chip used on a board. Change-Id: Id06766b4bac2686406bc09b8afa02f311f40dee7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11798 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/bd82x6x/chip.h3
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c17
2 files changed, 20 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 3fa9192a40..41adc9a7f0 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -96,6 +96,9 @@ struct southbridge_intel_bd82x6x_config {
uint32_t superspeed_capable_ports;
/* Overcurrent Mapping for USB 3.0 Ports */
uint32_t xhci_overcurrent_mapping;
+
+ uint32_t spi_uvscc;
+ uint32_t spi_lvscc;
};
#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 6bf43decef..a9e3ec56b5 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -480,6 +480,21 @@ static void pch_decode_init(struct device *dev)
pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec);
}
+static void pch_spi_init(const struct device *const dev)
+{
+ const config_t *const config = dev->chip_info;
+
+ printk(BIOS_DEBUG, "pch_spi_init\n");
+
+ if (config->spi_uvscc)
+ RCBA32(0x3800 + 0xc8) = config->spi_uvscc;
+ if (config->spi_lvscc)
+ RCBA32(0x3800 + 0xc4) = config->spi_lvscc;
+
+ if (config->spi_uvscc || config->spi_lvscc)
+ RCBA32_OR(0x3800 + 0xc4, 1 << 23); /* lock both UVSCC + LVSCC */
+}
+
static void lpc_init(struct device *dev)
{
printk(BIOS_DEBUG, "pch: lpc_init\n");
@@ -536,6 +551,8 @@ static void lpc_init(struct device *dev)
pch_set_acpi_mode();
pch_fixups(dev);
+
+ pch_spi_init(dev);
}
static void pch_lpc_read_resources(device_t dev)