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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-06-15 12:30:13 +0300 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-06-23 23:36:58 +0200 |
| commit | 81d3d7d00173eafff0ef134bdf1ee5e632f3868a (patch) | |
| tree | d7754384a76c329449de46d63586ad1717fffc4b /src/southbridge | |
| parent | dbc6fcd021759280c71b0e246c0ede34f4879bac (diff) | |
| download | coreboot-81d3d7d00173eafff0ef134bdf1ee5e632f3868a.tar.xz | |
lynxpoint: Fix early EHCI BAR programming
LynxPoint LP has only EHCI controller #1.
Change EHCI #2 to different BAR from EHCI #1.
Even if the ECHI controllers are not to be addressed, it is bad idea
to set two different devices to claim the same PCI memory cycles.
Change-Id: I95c59fb9d5f09afd152872e9bc0418dc67e4aeb2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3472
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_usb.c | 26 |
1 files changed, 11 insertions, 15 deletions
diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index ebd5c2c50a..d71467e066 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -34,23 +34,19 @@ * The BAR will be re-assigned during device * enumeration so these are only temporary. */ -void enable_usb_bar(void) +static void enable_usb_bar_on_device(device_t dev, u32 bar) { - device_t usb0 = PCH_EHCI1_DEV; - device_t usb1 = PCH_EHCI2_DEV; u32 cmd; - - /* USB Controller 1 */ - pci_write_config32(usb0, PCI_BASE_ADDRESS_0, - PCH_EHCI1_TEMP_BAR0); - cmd = pci_read_config32(usb0, PCI_COMMAND); + pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar); + cmd = pci_read_config32(dev, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb0, PCI_COMMAND, cmd); + pci_write_config32(dev, PCI_COMMAND, cmd); +} - /* USB Controller 1 */ - pci_write_config32(usb1, PCI_BASE_ADDRESS_0, - PCH_EHCI1_TEMP_BAR0); - cmd = pci_read_config32(usb1, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb1, PCI_COMMAND, cmd); +void enable_usb_bar(void) +{ + enable_usb_bar_on_device(PCH_EHCI1_DEV, PCH_EHCI1_TEMP_BAR0); +#if !CONFIG_INTEL_LYNXPOINT_LP + enable_usb_bar_on_device(PCH_EHCI2_DEV, PCH_EHCI2_TEMP_BAR0); +#endif } |