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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-23 17:10:27 +0200
committerMartin Roth <martinroth@google.com>2018-10-30 20:18:53 +0000
commit8a643703b87630b4346e52cac3d3acdc95ac1c70 (patch)
treee7ec84129a9c02940b8fd8bbd778601b15c0956a /src/southbridge
parent50f2e4ccec9df213e012c7ecddb0a9c644526c8d (diff)
downloadcoreboot-8a643703b87630b4346e52cac3d3acdc95ac1c70.tar.xz
{cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros
Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29243 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/rs780/gfx.c5
-rw-r--r--src/southbridge/amd/sr5650/sr5650.c4
2 files changed, 5 insertions, 4 deletions
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index a765655ce7..b17aebb0cc 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -34,6 +34,7 @@
#include <device/pci_ops.h>
#include <delay.h>
#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
#include "rs780.h"
/* Trust the original resource allocation. Don't do it again. */
@@ -762,11 +763,11 @@ static void rs780_internal_gfx_enable(struct device *dev)
printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev);
/* The system top memory in 780. */
- sysmem = rdmsr(0xc001001a);
+ sysmem = rdmsr(TOP_MEM);
printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo);
pci_write_config32(nb_dev, 0x90, sysmem.lo);
- sysmem = rdmsr(0xc001001D);
+ sysmem = rdmsr(TOP_MEM2);
printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo);
htiu_write_index(nb_dev, 0x31, sysmem.hi);
htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
index 1e85c48986..0f8b265781 100644
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -304,11 +304,11 @@ void sr5650_set_tom(struct device *nb_dev)
msr_t sysmem;
/* The system top memory in SR56X0. */
- sysmem = rdmsr(0xc001001A);
+ sysmem = rdmsr(TOP_MEM);
printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo);
pci_write_config32(nb_dev, 0x90, sysmem.lo);
- sysmem = rdmsr(0xc001001D);
+ sysmem = rdmsr(TOP_MEM2);
printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo);
htiu_write_index(nb_dev, 0x31, sysmem.hi);
htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);