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authorRonald G. Minnich <rminnich@gmail.com>2003-12-02 03:58:19 +0000
committerRonald G. Minnich <rminnich@gmail.com>2003-12-02 03:58:19 +0000
commit8aa7bccc9dcc51213f3b15f91f2d4985203f16dd (patch)
tree80524db1dbd56c3a2224e16c5ed4cd794e02091a /src/southbridge
parent13f8c07850ef34af891f0cffe287a0209b57f259 (diff)
downloadcoreboot-8aa7bccc9dcc51213f3b15f91f2d4985203f16dd.tar.xz
from Yh Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/amd8131/amd8131_bridge.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/southbridge/amd/amd8131/amd8131_bridge.c b/src/southbridge/amd/amd8131/amd8131_bridge.c
index 9d28de4f32..e730997bbc 100644
--- a/src/southbridge/amd/amd8131/amd8131_bridge.c
+++ b/src/southbridge/amd/amd8131/amd8131_bridge.c
@@ -69,6 +69,13 @@ static void ioapic_enable(device_t dev)
value &= ~((1 << 1) | (1 << 0));
}
pci_write_config32(dev, 0x44, value);
+
+//BY LYH
+ value = pci_read_config32(dev, 0x4);
+ value |= 6;
+ pci_write_config32(dev, 0x4, value);
+//BY LYH END
+
}
static struct device_operations ioapic_ops = {