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authorJonathan A. Kollasch <jakllsch@kollasch.net>2012-01-04 19:43:49 -0600
committerPeter Stuge <peter@stuge.se>2012-01-05 04:25:10 +0100
commit8bd41cd3b58ceb13b9b6670170bb8a90082a3c1e (patch)
tree04ca5c556cf69ac787ef8b65d97e776122407bc9 /src/southbridge
parentcb34bba5df7b081d5324d8af8c7ba4d5860ec9f8 (diff)
downloadcoreboot-8bd41cd3b58ceb13b9b6670170bb8a90082a3c1e.tar.xz
rs780: power down GPPSB SB lane pads in correct PCIe core
Change-Id: I059d5b155cae051f31cc2495f8a47d53e01af808 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/519 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/rs780/pcie.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c
index 5e2d985130..efa2e58e76 100644
--- a/src/southbridge/amd/rs780/pcie.c
+++ b/src/southbridge/amd/rs780/pcie.c
@@ -86,15 +86,21 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS +
PCIE_GFX_COMPLIANCE))) {
}
+
/* step 3 Power Down Control for Southbridge */
+ if (port != 8)
+ return;
+
reg = nbpcie_p_read_index(dev, 0xa2);
switch ((reg >> 4) & 0x7) { /* get bit 4-6, LC_LINK_WIDTH_RD */
case 1:
- nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e);
+ set_pcie_enable_bits(nb_dev, 0x65 | PCIE_CORE_INDEX_GPPSB,
+ 0x0f0f, 0x0e0e);
break;
case 2:
- nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c);
+ set_pcie_enable_bits(nb_dev, 0x65 | PCIE_CORE_INDEX_GPPSB,
+ 0x0f0f, 0x0c0c);
break;
default:
break;