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authorArthur Heymans <arthur@aheymans.xyz>2018-09-11 22:26:13 +0200
committerFelix Held <felix-coreboot@felixheld.de>2018-10-15 12:50:50 +0000
commit8ddd7d1e5eee9e3e604624622d9b91f9b99306ff (patch)
tree8d7757bb8aab83658ea6e7b2069b15eb8ef8f203 /src/southbridge
parent672d5ad20b8c9aab677e754dc2996f1e5a30cb77 (diff)
downloadcoreboot-8ddd7d1e5eee9e3e604624622d9b91f9b99306ff.tar.xz
nb/intel/x4x: Program read training results to all ranks
While during the read training itself only the settings for rank 0 are used for all ranks, the controller does use the separate settings for each rank later on. It is unknown which register is responsible for this. The signals are probably not generated separately and therefore need to have the same settings for all ranks. Therefore program the results for all ranks instead of for all populated ranks. TESTED: Fixes DG43GT not booting with only the second DIMM slot of a channel populated. Change-Id: I7965a068ef4779847e62e966154764370c91302a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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