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authorSubrata Banik <subrata.banik@intel.com>2020-08-30 13:51:44 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-09-01 03:06:04 +0000
commit8e6d5f2937c169914e46b5ebc973e5df5e4290a7 (patch)
tree1550c8877877a7a9b197da65bcff76f878bee560 /src/southbridge
parentb7a68d5b05259a07a84a546e6a7e40948ba705ac (diff)
downloadcoreboot-8e6d5f2937c169914e46b5ebc973e5df5e4290a7.tar.xz
{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent
Convert 0X -> 0x Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index c6944ede9a..2a3b167944 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -89,9 +89,9 @@ void i82371eb_early_init(void);
#define PMBA 0x40 /* Power management base address */
#define DEFAULT_PMBASE 0xe400
#define PM_IO_BASE DEFAULT_PMBASE
-#define DEVRESA 0X5c /* Device resource A */
-#define DEVRESB 0X60 /* Device resource B */
-#define DEVRESC 0X64 /* Device resource C */
+#define DEVRESA 0x5c /* Device resource A */
+#define DEVRESB 0x60 /* Device resource B */
+#define DEVRESC 0x64 /* Device resource C */
#define DEVRESD 0x52 /* Device resource D */
#define DEVRESE 0x68 /* Device resource E */
#define DEVRESF 0x6c /* Device resource F */