summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
authorTimothy Pearson <tpearson@raptorengineeringinc.com>2016-04-04 14:24:23 -0500
committerMartin Roth <martinroth@google.com>2016-04-05 22:37:46 +0200
commit9ef671769bc5be393f356c85359909a56145a912 (patch)
tree892a10d2391b8df86a3841bb07891473b1a1046d /src/southbridge
parent1000a5561d0c122e3800896b36767f09f3d96901 (diff)
downloadcoreboot-9ef671769bc5be393f356c85359909a56145a912.tar.xz
sb/amd/sp5100: Add ehci_async_data_cache CMOS option
SP5100 devices are affected by an erratum that can lock up the EHCI ports under certain conditions. Add an optional CMOS option to enable a workaround at the expense of performance. Change-Id: I305d23dfa50f10a3dcb5c731e8923305c8956dde Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14241 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/sb700/usb.c17
1 files changed, 15 insertions, 2 deletions
diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c
index cd7378e7b8..0fdff78f44 100644
--- a/src/southbridge/amd/sb700/usb.c
+++ b/src/southbridge/amd/sb700/usb.c
@@ -20,6 +20,7 @@
#include <device/pci_ops.h>
#include <device/pci_ehci.h>
#include <arch/io.h>
+#include <option.h>
#include "sb700.h"
static struct pci_operations lops_pci = {
@@ -76,10 +77,16 @@ static void usb_init(struct device *dev)
static void usb_init2(struct device *dev)
{
- u32 dword;
+ uint32_t dword;
void *usb2_bar0;
device_t sm_dev;
- u8 rev;
+ uint8_t rev;
+ uint8_t ehci_async_data_cache;
+ uint8_t nvram;
+
+ ehci_async_data_cache = 1;
+ if (get_option(&nvram, "ehci_async_data_cache") == CB_SUCCESS)
+ ehci_async_data_cache = !!nvram;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
rev = get_sb700_revision(sm_dev);
@@ -174,6 +181,12 @@ static void usb_init2(struct device *dev)
dword |= 1 << 8;
dword &= ~(1 << 27); /* 6.23 */
}
+#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
+ /* SP5100 Erratum 36 */
+ dword &= ~(1 << 26);
+ if (!ehci_async_data_cache)
+ dword |= 1 << 26;
+#endif
pci_write_config32(dev, 0x50, dword);
printk(BIOS_DEBUG, "rpr 6.23, final dword=%x\n", dword);
}