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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-09 08:08:58 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-10 11:17:40 +0000 |
| commit | a244d5edd4f45fd9e21db3d97ed0a32eaf089e7b (patch) | |
| tree | f3d714cc53ceddf0cbb7319551bd8859bc52e356 /src/southbridge | |
| parent | 0a2de7b538e3d6490a8d748bc8b8b9b7511c81bc (diff) | |
| download | coreboot-a244d5edd4f45fd9e21db3d97ed0a32eaf089e7b.tar.xz | |
sb/amd/{agesa,pi}/hudson: Explicitly enable LPC controller
Location in hudson_lpc_port80() was called conditionally.
Also move hudson_lpc_decode() call after enable_acpimmio_decode_pmXX()
due the change from IO to MMIO using pm_read/write.
Change-Id: I38e94e4b04f0a493052cfd3ffdd0a9c2ac0d07fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/bootblock.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/early_setup.c | 11 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/bootblock.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/early_setup.c | 11 |
4 files changed, 10 insertions, 16 deletions
diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 6925393b06..4da030b89a 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -74,8 +74,8 @@ void bootblock_soc_early_init(void) u32 data; bootblock_southbridge_init(); - hudson_lpc_decode(); enable_acpimmio_decode_pm24(); + hudson_lpc_decode(); if (CONFIG(POST_DEVICE_PCI_PCIE)) hudson_pci_port80(); diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index d85cb2b6f1..84c429955a 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> +#include <amdblocks/acpimmio.h> #include "hudson.h" @@ -73,13 +74,6 @@ void hudson_lpc_port80(void) u8 byte; pci_devfn_t dev; - /* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); - /* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x4a); @@ -92,6 +86,9 @@ void hudson_lpc_decode(void) pci_devfn_t dev; u32 tmp; + /* Enable LPC controller */ + pm_write8(0xec, pm_read8(0xec) | 0x01); + dev = PCI_DEV(0, 0x14, 3); /* Serial port numeration on Hudson: * PORT0 - 0x3f8 diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index ec8663dad1..d16aecc2a8 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -73,11 +73,11 @@ void bootblock_soc_early_init(void) u32 data; bootblock_southbridge_init(); - hudson_lpc_decode(); if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)) enable_acpimmio_decode_pm24(); else enable_acpimmio_decode_pm04(); + hudson_lpc_decode(); if (CONFIG(POST_DEVICE_PCI_PCIE)) hudson_pci_port80(); diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 56b894c852..0e3646bb5c 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -22,6 +22,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> +#include <amdblocks/acpimmio.h> #include "hudson.h" #include "pci_devs.h" @@ -106,13 +107,6 @@ void hudson_lpc_port80(void) u8 byte; pci_devfn_t dev; - /* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); - /* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x4a); @@ -125,6 +119,9 @@ void hudson_lpc_decode(void) pci_devfn_t dev; u32 tmp; + /* Enable LPC controller */ + pm_write8(0xec, pm_read8(0xec) | 0x01); + dev = PCI_DEV(0, 0x14, 3); /* Serial port numeration on Hudson: * PORT0 - 0x3f8 |