summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
authorSven Schnelle <svens@stackframe.org>2012-01-31 22:40:50 +0100
committerSven Schnelle <svens@stackframe.org>2012-01-31 23:31:41 +0100
commitab46c15f61844b62ded575d5710fe2da0cae32d8 (patch)
treee144da83043208b0d5993127f7f1bd92bc7b25a5 /src/southbridge
parent7363ca35f06f3a3ac398812812b75118aab8c6bf (diff)
downloadcoreboot-ab46c15f61844b62ded575d5710fe2da0cae32d8.tar.xz
i3100: Add init sequence
i3100 misses the magic SATA init sequence, which makes all requests fail. Captured from the vendor BIOS, which writes those bits on all configurations. Change-Id: I293b7d9cd681181311ecaced6d7df9b2706c711f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/600 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/i3100/sata.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c
index af22600f90..1925f888ed 100644
--- a/src/southbridge/intel/i3100/sata.c
+++ b/src/southbridge/intel/i3100/sata.c
@@ -81,6 +81,24 @@ static void sata_init(struct device *dev)
pci_write_config8(dev, SATA_PCS + 1, 0x0f);
}
+
+ /* secret init sequence, required */
+ pci_write_config32(dev, 0x94, 0x00400180);
+ pci_write_config32(dev, 0xa0, 0x18);
+ pci_write_config32(dev, 0xa4, 0x224);
+ pci_write_config32(dev, 0xa0, 0x42);
+ pci_write_config32(dev, 0xa4, 0x22006d);
+ pci_write_config32(dev, 0xa0, 0x84);
+ pci_write_config32(dev, 0xa4, 0x24);
+ pci_write_config32(dev, 0xa0, 0x7a);
+ pci_write_config32(dev, 0xa4, 0x220000);
+ pci_write_config32(dev, 0xa0, 0x9c);
+ pci_write_config32(dev, 0xa4, 0x24);
+ pci_write_config32(dev, 0xa0, 0x90);
+ pci_write_config32(dev, 0xa4, 0x220000);
+ pci_write_config32(dev, 0xa0, 0xa0);
+ pci_write_config32(dev, 0xa4, 0x12492aa);
+
printk(BIOS_DEBUG, "SATA Enabled\n");
}