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authorStefan Reinauer <stepan@coresystems.de>2010-04-25 13:54:30 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-25 13:54:30 +0000
commitd55e26f1b1efe50aa013ad32bdf3e2b58101a64f (patch)
tree08e5801c91c46eb3837b90c1828fb7f4b96c0479 /src/southbridge
parent7d2a39631efa117d7a5e89810e905a838789518f (diff)
downloadcoreboot-d55e26f1b1efe50aa013ad32bdf3e2b58101a64f.tar.xz
zero warnings days
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5492 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/rs780/rs780_gfx.c2
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c26
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c18
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_early_smbus.c30
4 files changed, 38 insertions, 38 deletions
diff --git a/src/southbridge/amd/rs780/rs780_gfx.c b/src/southbridge/amd/rs780/rs780_gfx.c
index 90dc0cd29a..b1dd762ec5 100644
--- a/src/southbridge/amd/rs780/rs780_gfx.c
+++ b/src/southbridge/amd/rs780/rs780_gfx.c
@@ -122,6 +122,7 @@ static void FreeMMIO(MMIORANGE* pMMIO)
#define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1
#define MMIO_ATTRIB_SKIP_ZERO 1<<2
+#ifdef DONT_TRUST_RESOURCE_ALLOCATION
static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
{
int i;
@@ -180,7 +181,6 @@ static u8 FinalizeMMIO(MMIORANGE *pMMIO)
return n;
}
-#ifdef DONT_TRUST_RESOURCE_ALLOCATION
static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
{
CIM_STATUS Status = CIM_UNSUPPORTED;
diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c b/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c
index 4e5e2e729a..3b5a507538 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c
@@ -19,6 +19,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <reset.h>
+
static unsigned get_sbdn(unsigned bus)
{
device_t dev;
@@ -33,7 +35,15 @@ static unsigned get_sbdn(unsigned bus)
}
-static void hard_reset(void)
+void soft_reset(void)
+{
+ set_bios_reset();
+ /* link reset */
+ outb(0x02, 0x0cf9);
+ outb(0x06, 0x0cf9);
+}
+
+void hard_reset(void)
{
set_bios_reset();
@@ -41,20 +51,10 @@ static void hard_reset(void)
outb(0x0a, 0x0cf9);
outb(0x0e, 0x0cf9);
}
+
static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
{
-/* default value for mcp55 is good */
+ /* default value for mcp55 is good */
/* set VFSMAF ( VID/FID System Management Action Field) to 2 */
-
-}
-
-static void soft_reset(void)
-{
- set_bios_reset();
-#if 1
- /* link reset */
- outb(0x02, 0x0cf9);
- outb(0x06, 0x0cf9);
-#endif
}
diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
index 06d9f273c4..60337d1635 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
@@ -21,6 +21,7 @@
static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val);
+#ifdef UNUSED_CODE
static int set_ht_link_mcp55(uint8_t ht_c_num)
{
unsigned vendorid = 0x10de;
@@ -51,6 +52,7 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, con
outl(val, control);
}
+#endif
/* SIZE 0x100 */
#define ANACTRL_IO_BASE 0x2800
@@ -131,14 +133,6 @@ static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, unsigned
}
-static void delayx(uint8_t value) {
-#if 1
- int i;
- for(i=0;i<0x8000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x)
{
@@ -169,15 +163,15 @@ static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anac
tgio_ctrl |= (pci_e_x<<4)|(1<<8);
outl(tgio_ctrl, anactrl_io_base + 0xcc);
-// wait 100us
- delayx(1);
+ // wait 100us
+ udelay(100);
dword = pci_read_config32(dev, 0xe4);
dword &= ~(0x3f0); // enable
pci_write_config32(dev, 0xe4, dword);
-// need to wait 100ms
- delayx(1000);
+ // need to wait 100ms
+ mdelay(100);
}
static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x)
diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c b/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
index 83ea61965b..80a06188f1 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
@@ -31,13 +31,13 @@ static void enable_smbus(void)
{
device_t dev;
dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0);
-#if 0
+
if (dev == PCI_DEV_INVALID) {
- die("SMBUS controller not found\n");
+ printk(BIOS_WARNING, "SMBUS controller not found\n");
+ } else {
+ printk(BIOS_DEBUG, "SMBus controller enabled\n");
}
- print_debug("SMBus controller enabled\n");
-#endif
/* set smbus iobase */
pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1);
pci_write_config32(dev, 0x24, SMBUS1_IO_BASE | 1);
@@ -48,36 +48,42 @@ static void enable_smbus(void)
outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT);
}
-static int smbus_recv_byte(unsigned device)
+static inline int smbus_recv_byte(unsigned device)
{
return do_smbus_recv_byte(SMBUS0_IO_BASE, device);
}
-static int smbus_send_byte(unsigned device, unsigned char val)
+
+static inline int smbus_send_byte(unsigned device, unsigned char val)
{
return do_smbus_send_byte(SMBUS0_IO_BASE, device, val);
}
-static int smbus_read_byte(unsigned device, unsigned address)
+
+static inline int smbus_read_byte(unsigned device, unsigned address)
{
return do_smbus_read_byte(SMBUS0_IO_BASE, device, address);
}
-static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
+
+static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
{
return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val);
}
-static int smbusx_recv_byte(unsigned smb_index, unsigned device)
+static inline int smbusx_recv_byte(unsigned smb_index, unsigned device)
{
return do_smbus_recv_byte(SMBUS0_IO_BASE + (smb_index<<8), device);
}
-static int smbusx_send_byte(unsigned smb_index, unsigned device, unsigned char val)
+
+static inline int smbusx_send_byte(unsigned smb_index, unsigned device, unsigned char val)
{
return do_smbus_send_byte(SMBUS0_IO_BASE + (smb_index<<8), device, val);
}
-static int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address)
+
+static inline int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address)
{
return do_smbus_read_byte(SMBUS0_IO_BASE + (smb_index<<8), device, address);
}
-static int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address, unsigned char val)
+
+static inline int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address, unsigned char val)
{
return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index<<8), device, address, val);
}