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authorNathaniel Roach <nroach44@gmail.com>2017-09-09 19:59:07 +0800
committerMartin Roth <martinroth@google.com>2017-09-19 01:27:17 +0000
commitd7e0cb93ae8ead42aa20dd4dcafa137fc28653bc (patch)
tree13e0580e5f4d75ac145bda0a7152b3e9ff8d1a6c /src/southbridge
parent2fd9651b239498a95c749ad3da140aa4d2cb06b8 (diff)
downloadcoreboot-d7e0cb93ae8ead42aa20dd4dcafa137fc28653bc.tar.xz
sb/intel/bd82x6x: Add awareness of ME's Alt Disable Mode
me_cleaner now allows setting a bit in the PCH straps - AltMeDisable tells the ME to stop execution after BUP - disabling the 30 minute watchdog - but also "breaking" the ME. The ME reports opmode = 2. This means the ME will not respond when we wait for an acknowledgement about the DRAM being ready. The current code waits 5 seconds for a response, that in this case, never comes. If the ME is reporting opmode 2, don't delay or wait for a response from the ME. Tested on my X220, this patch fixed the five seconds before the payload executed. Verified using the timestamp patch. Change-Id: Ifdda6b2dbb8ae3a650be6d5df6c60475a3fa74aa Signed-off-by: Nathaniel Roach <nroach44@gmail.com> Reviewed-on: https://review.coreboot.org/21466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/bd82x6x/early_me.c28
-rw-r--r--src/southbridge/intel/bd82x6x/me_status.c2
2 files changed, 19 insertions, 11 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c
index b2e920056d..47b8708ba7 100644
--- a/src/southbridge/intel/bd82x6x/early_me.c
+++ b/src/southbridge/intel/bd82x6x/early_me.c
@@ -191,18 +191,26 @@ int intel_early_me_init_done(u8 status)
meDID = did.uma_base | (1 << 28);// | (1 << 23);
pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_ME_H_GS, meDID);
- timestamp_add_now(TS_ME_INFORM_DRAM_WAIT);
- udelay(1100);
-
/* Must wait for ME acknowledgement */
- millisec = 0;
- hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;
- while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK) && (millisec < 5000)) {
- udelay(1000);
- hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;
- millisec++;
+ if (opmode == ME_HFS_MODE_DEBUG) {
+ printk(BIOS_NOTICE,
+ "ME: ME is reporting as disabled, "
+ "so not waiting for a response.\n");
+ } else {
+ timestamp_add_now(TS_ME_INFORM_DRAM_WAIT);
+ udelay(100);
+ millisec = 0;
+ do {
+ udelay(1000);
+ hfs = (pci_read_config32(
+ PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000)
+ >> 24;
+ millisec++;
+ } while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK)
+ && (millisec <= 5000));
+ timestamp_add_now(TS_ME_INFORM_DRAM_DONE);
}
- timestamp_add_now(TS_ME_INFORM_DRAM_DONE);
+
me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c
index 8669429073..b202376653 100644
--- a/src/southbridge/intel/bd82x6x/me_status.c
+++ b/src/southbridge/intel/bd82x6x/me_status.c
@@ -43,7 +43,7 @@ static const char *me_opstate_values[] = {
/* HFS[19:16] Current Operation Mode Values */
static const char *me_opmode_values[] = {
[ME_HFS_MODE_NORMAL] = "Normal",
- [ME_HFS_MODE_DEBUG] = "Debug",
+ [ME_HFS_MODE_DEBUG] = "Debug or Disabled by AltDisableBit",
[ME_HFS_MODE_DIS] = "Soft Temporary Disable",
[ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper",
[ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message"