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authorElyes HAOUAS <ehaouas@noos.fr>2019-10-15 15:56:03 +0200
committerFelix Held <felix-coreboot@felixheld.de>2019-10-18 18:41:09 +0000
commitdf60e8786cd71c92a12156c381814b9234d52f6e (patch)
tree74bd9cfc6329c08cd60fc5a7bece34c32937b236 /src/southbridge
parentd9c799c5296c8f300031dafade682cf613ec4d34 (diff)
downloadcoreboot-df60e8786cd71c92a12156c381814b9234d52f6e.tar.xz
src: Remove unused include '<device/pci_ids.h>'
Change-Id: Ic90dcff9d0b49a75a26556e4a1884a2954ef68f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36063 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/cimx/sb800/early.c1
-rw-r--r--src/southbridge/amd/cimx/sb900/early.c1
-rw-r--r--src/southbridge/amd/pi/hudson/bootblock.c1
-rw-r--r--src/southbridge/intel/i82371eb/fadt.c1
4 files changed, 0 insertions, 4 deletions
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c
index 7d93c81dd8..48829578e1 100644
--- a/src/southbridge/amd/cimx/sb800/early.c
+++ b/src/southbridge/amd/cimx/sb800/early.c
@@ -14,7 +14,6 @@
*/
#include <stdint.h>
-#include <device/pci_ids.h>
#include "SBPLATFORM.h"
#include "sb_cimx.h"
#include "cfg.h" /*sb800_cimx_config*/
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index 1aa9a5a4ba..ccada12dc3 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -17,7 +17,6 @@
#define __SIMPLE_DEVICE__
#include <stdint.h>
-#include <device/pci_ids.h>
#include <arch/io.h>
#include "SbPlatform.h"
#include "sb_cimx.h"
diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c
index bdda5edbcc..f12cec8602 100644
--- a/src/southbridge/amd/pi/hudson/bootblock.c
+++ b/src/southbridge/amd/pi/hudson/bootblock.c
@@ -15,7 +15,6 @@
#include <stdint.h>
#include <device/pci_ops.h>
-#include <device/pci_ids.h>
/*
* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c
index 9e43e62065..cbfb0af2ee 100644
--- a/src/southbridge/intel/i82371eb/fadt.c
+++ b/src/southbridge/intel/i82371eb/fadt.c
@@ -21,7 +21,6 @@
#include <arch/acpi.h>
#include <device/device.h>
#include <device/pci.h>
-#include <device/pci_ids.h>
#include <version.h>
#include "i82371eb.h"