This patch unifies the use of config options in v2 to all start with CONFIG_

It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

45 files changed, 96 insertions, 96 deletions

diff --git a/src/southbridge/amd/amd8111/amd8111_acpi.c b/src/southbridge/amd/amd8111/amd8111_acpi.c
index 57c26910f8..9511474062 100644
--- a/src/southbridge/amd/amd8111/amd8111_acpi.c
+++ b/src/southbridge/amd/amd8111/amd8111_acpi.c
@@ -16,8 +16,8 @@
 #define SLOW_CPU_OFF 0
 #define SLOW_CPU__ON 1
 
-#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
 #endif
 
 
@@ -66,7 +66,7 @@ static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
 	return do_smbus_write_byte(res->base, device, address, val);
 }
 
-#if HAVE_ACPI_TABLES == 1
+#if CONFIG_HAVE_ACPI_TABLES == 1
 unsigned pm_base;
 #endif
 
@@ -112,7 +112,7 @@ static void acpi_init(struct device *dev)
 	pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5));
 	
 	/* power on after power fail */
-	on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 	get_option(&on, "power_on_after_fail");
 	byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 	byte &= ~0x40;
@@ -140,7 +140,7 @@ static void acpi_init(struct device *dev)
 				(on*12)+(on>>1),(on&1)*5);
 	}
 
-#if HAVE_ACPI_TABLES == 1
+#if CONFIG_HAVE_ACPI_TABLES == 1
 	pm_base = pci_read_config16(dev, 0x58) & 0xff00;
 	printk_debug("pm_base: 0x%04x\n",pm_base);
 #endif
diff --git a/src/southbridge/amd/cs5530/cs5530_pirq.c b/src/southbridge/amd/cs5530/cs5530_pirq.c
index edae7c9ab6..3fb9a74a1e 100644
--- a/src/southbridge/amd/cs5530/cs5530_pirq.c
+++ b/src/southbridge/amd/cs5530/cs5530_pirq.c
@@ -23,7 +23,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 
-#if (PIRQ_ROUTE==1 && HAVE_PIRQ_TABLE==1)
+#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_HAVE_PIRQ_TABLE==1)
 void pirq_assign_irqs(const unsigned char pIntAtoD[4])
 {
 	device_t pdev;
diff --git a/src/southbridge/amd/cs5536/cs5536_pirq.c b/src/southbridge/amd/cs5536/cs5536_pirq.c
index b8b4a10b1d..0723253898 100644
--- a/src/southbridge/amd/cs5536/cs5536_pirq.c
+++ b/src/southbridge/amd/cs5536/cs5536_pirq.c
@@ -23,7 +23,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 
-#if (PIRQ_ROUTE==1 && HAVE_PIRQ_TABLE==1)
+#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_HAVE_PIRQ_TABLE==1)
 void pirq_assign_irqs(const unsigned char pIntAtoD[4])
 {
 	device_t pdev;
diff --git a/src/southbridge/amd/sb600/sb600_early_setup.c b/src/southbridge/amd/sb600/sb600_early_setup.c
index e63e8e930e..b605b5e3bf 100644
--- a/src/southbridge/amd/sb600/sb600_early_setup.c
+++ b/src/southbridge/amd/sb600/sb600_early_setup.c
@@ -434,7 +434,7 @@ static void sb600_devices_por_init()
 
 	/*CIM set this register; but I didn't find its description in RPR.
 	On DBM690T platform, I didn't find different between set and skip this register.
-	But on Filbert platform, the DEBUG message from serial port on Peanut board can't be displayed
+	But on Filbert platform, the CONFIG_DEBUG message from serial port on Peanut board can't be displayed
 	after the bit0 of this register is set.
 	pci_write_config8(dev, 0x04, 0x21);
 	*/
diff --git a/src/southbridge/amd/sb600/sb600_sm.c b/src/southbridge/amd/sb600/sb600_sm.c
index a107d2dfd1..b0f99533a2 100644
--- a/src/southbridge/amd/sb600/sb600_sm.c
+++ b/src/southbridge/amd/sb600/sb600_sm.c
@@ -36,8 +36,8 @@
 #define MAINBOARD_POWER_OFF 0
 #define MAINBOARD_POWER_ON 1
 
-#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
 #endif
 
 struct ioapicreg {
@@ -164,7 +164,7 @@ static void sm_init(device_t dev)
 	pm_iowrite(0x53, byte);
 
 	/* power after power fail */
-	on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 	get_option(&on, "power_on_after_fail");
 	byte = pm_ioread(0x74);
 	byte &= ~0x03;
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
index dd11810483..2222102170 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
@@ -3,7 +3,7 @@
  *  by yinghai.lu@amd.com
  */
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 
 static void bcm5785_enable_rom(void)
 {
@@ -42,7 +42,7 @@ static void bcm5785_enable_lpc(void)
         byte |=(1<<1)|(1<<0);
         pci_write_config8(dev, 0x48, byte);
 }
-#endif /* USE_FALLBACK_IMAGE == 1 */
+#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
 
 
 static void bcm5785_enable_wdt_port_cf9(void)
diff --git a/src/southbridge/intel/i82801ca/cmos_failover.c b/src/southbridge/intel/i82801ca/cmos_failover.c
index 8eb11c3f64..bf35764c19 100644
--- a/src/southbridge/intel/i82801ca/cmos_failover.c
+++ b/src/southbridge/intel/i82801ca/cmos_failover.c
@@ -4,7 +4,7 @@
 
 static void check_cmos_failed(void) 
 {
-#if HAVE_OPTION_TABLE
+#if CONFIG_HAVE_OPTION_TABLE
 	uint8_t byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
 
 	if( byte & RTC_BATTERY_DEAD) {
@@ -12,7 +12,7 @@ static void check_cmos_failed(void)
 		// clear reboot_bits
         byte = cmos_read(RTC_BOOT_BYTE);
         byte &= 0x0c;
-        byte |= MAX_REBOOT_CNT << 4;
+        byte |= CONFIG_MAX_REBOOT_CNT << 4;
         cmos_write(byte, RTC_BOOT_BYTE);
     }
 #endif
diff --git a/src/southbridge/intel/i82801ca/i82801ca_lpc.c b/src/southbridge/intel/i82801ca/i82801ca_lpc.c
index b249438a1f..69535bc016 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_lpc.c
+++ b/src/southbridge/intel/i82801ca/i82801ca_lpc.c
@@ -15,8 +15,8 @@
 
 #define NMI_OFF 0
 
-#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
 #endif
 
 #define MAINBOARD_POWER_OFF 0
@@ -88,7 +88,7 @@ void i82801ca_rtc_init(struct device *dev)
 {
     uint32_t dword;
     int rtc_failed;
-	int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
     uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
 
     rtc_failed = pmcon3 & RTC_BATTERY_DEAD;
diff --git a/src/southbridge/intel/i82801dbm/cmos_failover.c b/src/southbridge/intel/i82801dbm/cmos_failover.c
index 9702313f9c..4821fad3d2 100644
--- a/src/southbridge/intel/i82801dbm/cmos_failover.c
+++ b/src/southbridge/intel/i82801dbm/cmos_failover.c
@@ -10,7 +10,7 @@ static void check_cmos_failed(void)
 //clear bit 1 and bit 2
                         byte = cmos_read(RTC_BOOT_BYTE);
                         byte &= 0x0c;
-                        byte |= MAX_REBOOT_CNT << 4;
+                        byte |= CONFIG_MAX_REBOOT_CNT << 4;
                         cmos_write(byte, RTC_BOOT_BYTE);
                 }
 }
diff --git a/src/southbridge/intel/i82801er/cmos_failover.c b/src/southbridge/intel/i82801er/cmos_failover.c
index 9702313f9c..4821fad3d2 100644
--- a/src/southbridge/intel/i82801er/cmos_failover.c
+++ b/src/southbridge/intel/i82801er/cmos_failover.c
@@ -10,7 +10,7 @@ static void check_cmos_failed(void)
 //clear bit 1 and bit 2
                         byte = cmos_read(RTC_BOOT_BYTE);
                         byte &= 0x0c;
-                        byte |= MAX_REBOOT_CNT << 4;
+                        byte |= CONFIG_MAX_REBOOT_CNT << 4;
                         cmos_write(byte, RTC_BOOT_BYTE);
                 }
 }
diff --git a/src/southbridge/intel/i82801er/i82801er_lpc.c b/src/southbridge/intel/i82801er/i82801er_lpc.c
index 02d474e8d5..fa89469693 100644
--- a/src/southbridge/intel/i82801er/i82801er_lpc.c
+++ b/src/southbridge/intel/i82801er/i82801er_lpc.c
@@ -18,8 +18,8 @@
 #define MAINBOARD_POWER_OFF 0
 #define MAINBOARD_POWER_ON  1
 
-#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
 #endif
 
 #define ALL		(0xff << 24)
@@ -283,7 +283,7 @@ static void lpc_init(struct device *dev)
 {
 	uint8_t byte;
 	uint32_t value;
-	int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 
 	/* IO APIC initialization */
 	value = pci_read_config32(dev, 0xd0);
diff --git a/src/southbridge/intel/i82801gx/Config.lb b/src/southbridge/intel/i82801gx/Config.lb
index 53186ed293..9ef5f435e8 100644
--- a/src/southbridge/intel/i82801gx/Config.lb
+++ b/src/southbridge/intel/i82801gx/Config.lb
@@ -17,7 +17,7 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_SMI_HANDLER
+uses CONFIG_HAVE_SMI_HANDLER
 
 config chip.h
 driver i82801gx.o
@@ -36,7 +36,7 @@ driver i82801gx_usb_ehci.o
 object i82801gx_reset.o
 object i82801gx_watchdog.o
 
-if HAVE_SMI_HANDLER
+if CONFIG_HAVE_SMI_HANDLER
 	object i82801gx_smi.o
 	smmobject i82801gx_smihandler.o
 end
diff --git a/src/southbridge/intel/i82801gx/cmos_failover.c b/src/southbridge/intel/i82801gx/cmos_failover.c
index 0765404ceb..9eae0cbae7 100644
--- a/src/southbridge/intel/i82801gx/cmos_failover.c
+++ b/src/southbridge/intel/i82801gx/cmos_failover.c
@@ -31,7 +31,7 @@ static void check_cmos_failed(void)
 		// clear bit 1 and bit 2
 		byte = cmos_read(RTC_BOOT_BYTE);
 		byte &= 0x0c;
-		byte |= MAX_REBOOT_CNT << 4;
+		byte |= CONFIG_MAX_REBOOT_CNT << 4;
 		cmos_write(byte, RTC_BOOT_BYTE);
 	}
 }
diff --git a/src/southbridge/intel/i82801gx/i82801gx_azalia.c b/src/southbridge/intel/i82801gx/i82801gx_azalia.c
index fba46bae7c..d0f351413c 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_azalia.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_azalia.c
@@ -283,7 +283,7 @@ static void azalia_init(struct device *dev)
 	u8 reg8;
 	u32 reg32;
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 	// ESD
 	reg32 = pci_mmio_read_config32(dev, 0x134);
 	reg32 &= 0xff00ffff;
@@ -314,7 +314,7 @@ static void azalia_init(struct device *dev)
 	reg32 |= (0x80 << 0); // VCi map
 	pci_mmio_write_config32(dev, 0x120, reg32);
 #else
-#error ICH7 Azalia required MMCONF_SUPPORT
+#error ICH7 Azalia required CONFIG_MMCONF_SUPPORT
 #endif
 
 	/* Set Bus Master */
diff --git a/src/southbridge/intel/i82801gx/i82801gx_lpc.c b/src/southbridge/intel/i82801gx/i82801gx_lpc.c
index 241d610bdd..636b975669 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_lpc.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_lpc.c
@@ -185,7 +185,7 @@ static void i82801gx_power_options(device_t dev)
 	u8 reg8;
 	u16 reg16;
 
-	int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 	int nmi_option;
 
 	/* Which state do we want to goto after g3 (power restored)?
@@ -296,7 +296,7 @@ static void enable_clock_gating(void)
 	RCBA32(0x341c) = reg32;
 }
 
-#if HAVE_SMI_HANDLER
+#if CONFIG_HAVE_SMI_HANDLER
 static void i82801gx_lock_smm(struct device *dev)
 {
 	void smm_lock(void);
@@ -401,7 +401,7 @@ static void lpc_init(struct device *dev)
 
 	setup_i8259();
 
-#if HAVE_SMI_HANDLER
+#if CONFIG_HAVE_SMI_HANDLER
 	i82801gx_lock_smm(dev);
 #endif
 
diff --git a/src/southbridge/intel/i82801gx/i82801gx_pci.c b/src/southbridge/intel/i82801gx/i82801gx_pci.c
index 2bf228b135..bf252ec37e 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_pci.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_pci.c
@@ -72,11 +72,11 @@ static void ich_pci_dev_enable_resources(struct device *dev)
 	if (dev->on_mainboard && ops && ops->set_subsystem) {
 		printk_debug("%s subsystem <- %02x/%02x\n",
 			dev_path(dev), 
-			MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
-			MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
 		ops->set_subsystem(dev, 
-			MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
-			MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
 	}
 
 	command = pci_read_config16(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/i82801gx/i82801gx_pcie.c b/src/southbridge/intel/i82801gx/i82801gx_pcie.c
index 6965b30972..d7655c5ea5 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_pcie.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_pcie.c
@@ -55,7 +55,7 @@ static void pci_init(struct device *dev)
 	reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
 	pci_write_config32(dev, 0xe1, reg32);
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 	/* Set VC0 transaction class */
 	reg32 = pci_mmio_read_config32(dev, 0x114);
 	reg32 &= 0xffffff00;
diff --git a/src/southbridge/intel/i82801xx/cmos_failover.c b/src/southbridge/intel/i82801xx/cmos_failover.c
index 2ff632548b..9307f40305 100644
--- a/src/southbridge/intel/i82801xx/cmos_failover.c
+++ b/src/southbridge/intel/i82801xx/cmos_failover.c
@@ -26,7 +26,7 @@ static void check_cmos_failed(void)
 		//clear bit 1 and bit 2
 		byte = cmos_read(RTC_BOOT_BYTE);
 		byte &= 0x0c;
-		byte |= MAX_REBOOT_CNT << 4;
+		byte |= CONFIG_MAX_REBOOT_CNT << 4;
 		cmos_write(byte, RTC_BOOT_BYTE);
 	}
 }
diff --git a/src/southbridge/nvidia/ck804/Config.lb b/src/southbridge/nvidia/ck804/Config.lb
index 481ced004d..36682984e6 100644
--- a/src/southbridge/nvidia/ck804/Config.lb
+++ b/src/southbridge/nvidia/ck804/Config.lb
@@ -1,4 +1,4 @@
-uses HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_TABLES
 
 config chip.h
 driver ck804.o
@@ -15,6 +15,6 @@ driver ck804_pcie.o
 driver ck804_ht.o
 object ck804_reset.o
 
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
 	object ck804_fadt.o
 end
diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup.c b/src/southbridge/nvidia/ck804/ck804_early_setup.c
index 0632197c7c..0d8a630d7a 100644
--- a/src/southbridge/nvidia/ck804/ck804_early_setup.c
+++ b/src/southbridge/nvidia/ck804/ck804_early_setup.c
@@ -71,13 +71,13 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
 
 #define CK804_CHIP_REV 3
 
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
+#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
 #else
-#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
+#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
-#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
 #define CK804B_DEVN_BASE 1
 #else
 #define CK804B_DEVN_BASE CK804_DEVN_BASE
diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
index cec869fae5..3e2a69a164 100644
--- a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
@@ -78,13 +78,13 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
 
 #define CK804_CHIP_REV 3
 
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
+#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
 #else
-#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
+#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
-#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
 #define CK804B_DEVN_BASE 1
 #else
 #define CK804B_DEVN_BASE CK804_DEVN_BASE
diff --git a/src/southbridge/nvidia/ck804/ck804_enable_rom.c b/src/southbridge/nvidia/ck804/ck804_enable_rom.c
index fac0da5a3a..8e2b29d61d 100644
--- a/src/southbridge/nvidia/ck804/ck804_enable_rom.c
+++ b/src/southbridge/nvidia/ck804/ck804_enable_rom.c
@@ -3,10 +3,10 @@
  *  by yhlu@tyan.com
  */
 
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
+#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
 #else
-#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
+#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
 static void ck804_enable_rom(void)
diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/ck804_lpc.c
index db7c29ba84..bb2cf99401 100644
--- a/src/southbridge/nvidia/ck804/ck804_lpc.c
+++ b/src/southbridge/nvidia/ck804/ck804_lpc.c
@@ -108,8 +108,8 @@ static void setup_ioapic(unsigned long ioapic_base)
 #define SLOW_CPU_OFF 0
 #define SLOW_CPU__ON 1
 
-#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
 #endif
 
 static void lpc_common_init(device_t dev)
@@ -198,7 +198,7 @@ static void lpc_init(device_t dev)
 #endif
 
 	/* power after power fail */
-	on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 	get_option(&on, "power_on_after_fail");
 	byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 	byte &= ~0x40;
diff --git a/src/southbridge/nvidia/ck804/id.inc b/src/southbridge/nvidia/ck804/id.inc
index 5c0991871b..d8e26ebde4 100644
--- a/src/southbridge/nvidia/ck804/id.inc
+++ b/src/southbridge/nvidia/ck804/id.inc
@@ -3,12 +3,12 @@
 	.globl __id_start
 __id_start:
 vendor:
-	.asciz MAINBOARD_VENDOR
+	.asciz CONFIG_MAINBOARD_VENDOR
 part:
-	.asciz MAINBOARD_PART_NUMBER
+	.asciz CONFIG_MAINBOARD_PART_NUMBER
 .long __id_end + 0x80 - vendor       /* Reverse offset to the vendor ID */
 .long __id_end + 0x80 - part         /* Reverse offset to the part number */
-.long PAYLOAD_SIZE + ROM_IMAGE_SIZE  /* Size of this ROM image */
+.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE  /* Size of this ROM image */
 	.globl __id_end
 
 __id_end:
diff --git a/src/southbridge/nvidia/ck804/id.lds b/src/southbridge/nvidia/ck804/id.lds
index 947a2f0c03..d95b9afcf4 100644
--- a/src/southbridge/nvidia/ck804/id.lds
+++ b/src/southbridge/nvidia/ck804/id.lds
@@ -1,5 +1,5 @@
 SECTIONS {
-	. = (_ROMBASE + ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
+	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
 	.id (.): {
 		*(.id)
 	}
diff --git a/src/southbridge/nvidia/ck804/romstrap.lds b/src/southbridge/nvidia/ck804/romstrap.lds
index 5b69024629..f26299f69f 100644
--- a/src/southbridge/nvidia/ck804/romstrap.lds
+++ b/src/southbridge/nvidia/ck804/romstrap.lds
@@ -1,5 +1,5 @@
 SECTIONS {
-	. = (_ROMBASE + ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start);
+	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start);
 	.romstrap (.): {
 		*(.romstrap)
 	}
diff --git a/src/southbridge/nvidia/mcp55/Config.lb b/src/southbridge/nvidia/mcp55/Config.lb
index f84fde780f..492cd3fdf9 100644
--- a/src/southbridge/nvidia/mcp55/Config.lb
+++ b/src/southbridge/nvidia/mcp55/Config.lb
@@ -19,7 +19,7 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ## 
 
-uses HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_TABLES
 
 config chip.h
 driver mcp55.o
@@ -35,6 +35,6 @@ driver mcp55_pci.o
 driver mcp55_pcie.o
 driver mcp55_ht.o
 object mcp55_reset.o
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
 	object mcp55_fadt.o
 end
diff --git a/src/southbridge/nvidia/mcp55/id.inc b/src/southbridge/nvidia/mcp55/id.inc
index ad386e7eee..880ae4b766 100644
--- a/src/southbridge/nvidia/mcp55/id.inc
+++ b/src/southbridge/nvidia/mcp55/id.inc
@@ -24,12 +24,12 @@
 	.globl __id_start
 __id_start:
 vendor:
-	.asciz MAINBOARD_VENDOR
+	.asciz CONFIG_MAINBOARD_VENDOR
 part:
-	.asciz MAINBOARD_PART_NUMBER
+	.asciz CONFIG_MAINBOARD_PART_NUMBER
 .long __id_end + 0x80 - vendor  /* Reverse offset to the vendor id */
 .long __id_end + 0x80 - part    /* Reverse offset to the part number */
-.long PAYLOAD_SIZE + ROM_IMAGE_SIZE  /* Size of this romimage */
+.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE  /* Size of this romimage */
 	.globl __id_end
 
 __id_end:
diff --git a/src/southbridge/nvidia/mcp55/id.lds b/src/southbridge/nvidia/mcp55/id.lds
index 668600a377..53215beb63 100644
--- a/src/southbridge/nvidia/mcp55/id.lds
+++ b/src/southbridge/nvidia/mcp55/id.lds
@@ -20,7 +20,7 @@
  */
 
 SECTIONS {
-	. = (_ROMBASE + ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
+	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
 	.id (.): {
 		*(.id)
 	}
diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c b/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
index 4bf0756f66..78e587e063 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
@@ -21,10 +21,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#if HT_CHAIN_END_UNITID_BASE != 0x20
-	#define MCP55_DEVN_BASE	HT_CHAIN_END_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
+	#define MCP55_DEVN_BASE	CONFIG_HT_CHAIN_END_UNITID_BASE
 #else
-	#define MCP55_DEVN_BASE	HT_CHAIN_UNITID_BASE
+	#define MCP55_DEVN_BASE	CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
 static void mcp55_enable_rom(void)
diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c
index 4775d9f516..1c7a26bffc 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c
@@ -21,10 +21,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#if HT_CHAIN_END_UNITID_BASE != 0x20
-	#define MCP55_DEVN_BASE	HT_CHAIN_END_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
+	#define MCP55_DEVN_BASE	CONFIG_HT_CHAIN_END_UNITID_BASE
 #else
-	#define MCP55_DEVN_BASE	HT_CHAIN_UNITID_BASE
+	#define MCP55_DEVN_BASE	CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
 #define EHCI_BAR_INDEX	0x10
diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c
index 4aff452958..4faaf08fe9 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c
@@ -132,8 +132,8 @@ static void setup_ioapic(unsigned long ioapic_base, int master)
 #define SLOW_CPU_OFF		0
 #define SLOW_CPU__ON		1
 
-#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
 #endif
 
 static void lpc_common_init(device_t dev, int master)
@@ -181,7 +181,7 @@ static void lpc_init(device_t dev)
 	/* power after power fail */
 
 #if 1
-	on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 	get_option(&on, "power_on_after_fail");
 	byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 	byte &= ~0x40;
diff --git a/src/southbridge/nvidia/mcp55/mcp55_smbus.c b/src/southbridge/nvidia/mcp55/mcp55_smbus.c
index cff22a3af7..484702ae64 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_smbus.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_smbus.c
@@ -94,7 +94,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
 	.write_byte	= lsmbus_write_byte,
 };
 
-#if HAVE_ACPI_TABLES == 1
+#if CONFIG_HAVE_ACPI_TABLES == 1
 unsigned pm_base;
 #endif
 
@@ -115,7 +115,7 @@ static void mcp55_sm_read_resources(device_t dev)
 
 static void mcp55_sm_init(device_t dev)
 {
-#if HAVE_ACPI_TABLES == 1
+#if CONFIG_HAVE_ACPI_TABLES == 1
 	struct resource *res;
 
 	res = find_resource(dev, 0x60);
diff --git a/src/southbridge/nvidia/mcp55/romstrap.lds b/src/southbridge/nvidia/mcp55/romstrap.lds
index 8a4efd49f1..c45f864152 100644
--- a/src/southbridge/nvidia/mcp55/romstrap.lds
+++ b/src/southbridge/nvidia/mcp55/romstrap.lds
@@ -20,7 +20,7 @@
  */
 
 SECTIONS {
-	. = (_ROMBASE + ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start);
+	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start);
 	.romstrap (.): {
 		*(.romstrap)
 	}
diff --git a/src/southbridge/sis/sis966/id.inc b/src/southbridge/sis/sis966/id.inc
index ad386e7eee..880ae4b766 100644
--- a/src/southbridge/sis/sis966/id.inc
+++ b/src/southbridge/sis/sis966/id.inc
@@ -24,12 +24,12 @@
 	.globl __id_start
 __id_start:
 vendor:
-	.asciz MAINBOARD_VENDOR
+	.asciz CONFIG_MAINBOARD_VENDOR
 part:
-	.asciz MAINBOARD_PART_NUMBER
+	.asciz CONFIG_MAINBOARD_PART_NUMBER
 .long __id_end + 0x80 - vendor  /* Reverse offset to the vendor id */
 .long __id_end + 0x80 - part    /* Reverse offset to the part number */
-.long PAYLOAD_SIZE + ROM_IMAGE_SIZE  /* Size of this romimage */
+.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE  /* Size of this romimage */
 	.globl __id_end
 
 __id_end:
diff --git a/src/southbridge/sis/sis966/id.lds b/src/southbridge/sis/sis966/id.lds
index 668600a377..53215beb63 100644
--- a/src/southbridge/sis/sis966/id.lds
+++ b/src/southbridge/sis/sis966/id.lds
@@ -20,7 +20,7 @@
  */
 
 SECTIONS {
-	. = (_ROMBASE + ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
+	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
 	.id (.): {
 		*(.id)
 	}
diff --git a/src/southbridge/sis/sis966/romstrap.lds b/src/southbridge/sis/sis966/romstrap.lds
index 8a4efd49f1..c45f864152 100644
--- a/src/southbridge/sis/sis966/romstrap.lds
+++ b/src/southbridge/sis/sis966/romstrap.lds
@@ -20,7 +20,7 @@
  */
 
 SECTIONS {
-	. = (_ROMBASE + ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start);
+	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start);
 	.romstrap (.): {
 		*(.romstrap)
 	}
diff --git a/src/southbridge/sis/sis966/sis966_enable_rom.c b/src/southbridge/sis/sis966/sis966_enable_rom.c
index 0e54694a95..63ef616563 100644
--- a/src/southbridge/sis/sis966/sis966_enable_rom.c
+++ b/src/southbridge/sis/sis966/sis966_enable_rom.c
@@ -23,10 +23,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-	#define SIS966_DEVN_BASE	HT_CHAIN_END_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
+	#define SIS966_DEVN_BASE	CONFIG_HT_CHAIN_END_UNITID_BASE
 #else
-	#define SIS966_DEVN_BASE	HT_CHAIN_UNITID_BASE
+	#define SIS966_DEVN_BASE	CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
 static void sis966_enable_rom(void)
diff --git a/src/southbridge/sis/sis966/sis966_enable_usbdebug_direct.c b/src/southbridge/sis/sis966/sis966_enable_usbdebug_direct.c
index 22f82f3ef2..f17a79e6c4 100644
--- a/src/southbridge/sis/sis966/sis966_enable_usbdebug_direct.c
+++ b/src/southbridge/sis/sis966/sis966_enable_usbdebug_direct.c
@@ -21,10 +21,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-	#define SIS966_DEVN_BASE	HT_CHAIN_END_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
+	#define SIS966_DEVN_BASE	CONFIG_HT_CHAIN_END_UNITID_BASE
 #else
-	#define SIS966_DEVN_BASE	HT_CHAIN_UNITID_BASE
+	#define SIS966_DEVN_BASE	CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
 #define EHCI_BAR_INDEX	0x10
diff --git a/src/southbridge/sis/sis966/sis966_lpc.c b/src/southbridge/sis/sis966/sis966_lpc.c
index 4e1b3cd5bc..6d3dd8e798 100644
--- a/src/southbridge/sis/sis966/sis966_lpc.c
+++ b/src/southbridge/sis/sis966/sis966_lpc.c
@@ -128,8 +128,8 @@ static void setup_ioapic(unsigned long ioapic_base)
 #define SLOW_CPU_OFF	0
 #define SLOW_CPU__ON	1
 
-#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL	MAINBOARD_POWER_ON
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL	MAINBOARD_POWER_ON
 #endif
 
 static void lpc_common_init(device_t dev)
@@ -179,7 +179,7 @@ static void lpc_init(device_t dev)
 	/* power after power fail */
 
 
-	on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 	get_option(&on, "power_on_after_fail");
 	byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 	byte &= ~0x40;
diff --git a/src/southbridge/via/k8t890/k8t890_dram.c b/src/southbridge/via/k8t890/k8t890_dram.c
index 5339257743..b32e5f870e 100644
--- a/src/southbridge/via/k8t890/k8t890_dram.c
+++ b/src/southbridge/via/k8t890/k8t890_dram.c
@@ -91,7 +91,7 @@ static void get_memres(void *gp, struct device *dev, struct resource *res)
 		(proposed_base < ((uint64_t) 0xffffffff) )) {
 		resmax = res;
 	}
-#if HAVE_HIGH_TABLES==1
+#if CONFIG_HAVE_HIGH_TABLES==1
 /* in arch/i386/boot/tables.c */
 extern uint64_t high_tables_base, high_tables_size;
 
diff --git a/src/southbridge/via/k8t890/romstrap.lds b/src/southbridge/via/k8t890/romstrap.lds
index ee162c37c8..6ce04f19ba 100644
--- a/src/southbridge/via/k8t890/romstrap.lds
+++ b/src/southbridge/via/k8t890/romstrap.lds
@@ -22,7 +22,7 @@
 /* Modified for K8T890 ROM strap by Rudolf Marek <r.marek@assembler.cz>. */
 
 SECTIONS {
-	. = (_ROMBASE + ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start);
+	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start);
 	.romstrap (.): {
 		*(.romstrap)
 	}
diff --git a/src/southbridge/via/vt8237r/Config.lb b/src/southbridge/via/vt8237r/Config.lb
index cca4a307ce..c127c5ab5f 100644
--- a/src/southbridge/via/vt8237r/Config.lb
+++ b/src/southbridge/via/vt8237r/Config.lb
@@ -17,7 +17,7 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_TABLES
 
 config chip.h
 
@@ -26,6 +26,6 @@ driver vt8237_ctrl.o
 driver vt8237r_ide.o
 driver vt8237r_lpc.o
 driver vt8237r_sata.o
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
 	object vt8237_fadt.o
 end
diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c
index fbcb5f3abe..1719fe09d8 100644
--- a/src/southbridge/via/vt8237r/vt8237r.c
+++ b/src/southbridge/via/vt8237r/vt8237r.c
@@ -33,7 +33,7 @@ void hard_reset(void)
 	printk_err("NO HARD RESET ON VT8237R! FIX ME!\n");
 }
 
-#if DEFAULT_CONSOLE_LOGLEVEL > 7
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 7
 void writeback(struct device *dev, u16 where, u8 what)
 {
 	u8 regval;
diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c
index 66cb3de77b..0711da8eb2 100644
--- a/src/southbridge/via/vt8237r/vt8237r_lpc.c
+++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c
@@ -225,7 +225,7 @@ static void setup_pm(device_t dev)
 
 	/* SCI is generated for RTC/pwrBtn/slpBtn. */
 	tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
-#if HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME == 1
 	acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
 	printk_debug("SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
 #endif