diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 17:28:05 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-20 19:06:04 +0000 |
| commit | 185691eedb37ae26f7829d762cd476395be57f5d (patch) | |
| tree | c13705dc09e24a407d5fa2af6f8bf2e6493582f7 /src/southbridge | |
| parent | 87bc7554478bc7a723baef0aedf5ad42e7747499 (diff) | |
| download | coreboot-185691eedb37ae26f7829d762cd476395be57f5d.tar.xz | |
sb/nvidia/ck804: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which platforms using this code lack.
Change-Id: I56cb6d0a04056b10af1e53afb697883329235c87
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36972
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
28 files changed, 0 insertions, 3333 deletions
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig deleted file mode 100644 index f931d4892b..0000000000 --- a/src/southbridge/nvidia/ck804/Kconfig +++ /dev/null @@ -1,41 +0,0 @@ -config SOUTHBRIDGE_NVIDIA_CK804 - bool - select HAVE_USBDEBUG - select IOAPIC - select HAVE_POWER_STATE_AFTER_FAILURE - -if SOUTHBRIDGE_NVIDIA_CK804 - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/nvidia/ck804/bootblock.c" - -config EHCI_BAR - hex - default 0xfef00000 - -config CK804_USE_NIC - bool - default n - -config CK804_USE_ACI - bool - default n - -config CK804_PCI_E_X - int - default 4 - -config CK804B_PCI_E_X - int - default 4 - -config CK804_PCIE_PME_WAKE - bool "Enable system wake on PCIe PME# signal" - default n - -config HPET_MIN_TICKS - hex - default 0xfa - -endif diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc deleted file mode 100644 index e74c70b180..0000000000 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ /dev/null @@ -1,28 +0,0 @@ -ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_CK804),y) - -ramstage-y += ck804.c -ramstage-y += usb.c -ramstage-y += lpc.c -ramstage-y += smbus.c -ramstage-y += ide.c -ramstage-y += sata.c -ramstage-y += usb2.c -ramstage-y += ac97.c -ramstage-y += nic.c -ramstage-y += pci.c -ramstage-y += pcie.c -ramstage-y += ht.c - -ramstage-y += reset.c - -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c - -bootblock-y += enable_usbdebug.c -romstage-y += enable_usbdebug.c -ramstage-y += enable_usbdebug.c -romstage-y += early_smbus.c - -bootblock-y += romstrap.ld -bootblock-y += romstrap.S - -endif diff --git a/src/southbridge/nvidia/ck804/ac97.c b/src/southbridge/nvidia/ck804/ac97.c deleted file mode 100644 index 28c5e74b2e..0000000000 --- a/src/southbridge/nvidia/ck804/ac97.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include "chip.h" - -static struct device_operations ac97audio_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver ac97audio_driver __pci_driver = { - .ops = &ac97audio_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_ACI, -}; - -static struct device_operations ac97modem_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver ac97modem_driver __pci_driver = { - .ops = &ac97modem_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_MCI, -}; diff --git a/src/southbridge/nvidia/ck804/acpi/ck804.asl b/src/southbridge/nvidia/ck804/acpi/ck804.asl deleted file mode 100644 index 4a83b8481e..0000000000 --- a/src/southbridge/nvidia/ck804/acpi/ck804.asl +++ /dev/null @@ -1,631 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (LPCB) { - Name (_ADR, 0x00010000) - OperationRegion (LPC0, PCI_Config, 0x00, 0x100) - Field (LPC0, AnyAcc, NoLock, Preserve) { - Offset (0x7c), - INTA, 4, INTB, 4, - INTC, 4, INTD, 4, - INTE, 4, INTF, 4, - INTG, 4, INTH, 4, - - INTI, 4, INTJ, 4, - INTK, 4, INTL, 4, - INTM, 4, INTN, 4, - INTO, 4, INTP, 4, - - INTQ, 4, INTR, 4, - INTS, 4, INTT, 4, - INTU, 4, INTV, 4, - INTW, 4, INTX, 4, - } -} - -/* set "A", 8259 interrupts */ -Name (PRSA, ResourceTemplate () { - IRQ(Level, ActiveLow, Shared) {5, 7, 10, 11} -}) -Method (CRSA, 1, Serialized) { - Name (LRTL, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(LRTL, 1, LIRQ) - ShiftLeft(1, Arg0, LIRQ) - Return (LRTL) -} -Method (SRSA, 1, Serialized) { - CreateWordField(Arg0, 1, LIRQ) - FindSetRightBit(LIRQ, Local0) - Decrement(Local0) - Return (Local0) -} - -/* set "B", external (PCI) APIC interrupts */ -Name (PRSB, ResourceTemplate () { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) { - 16, 17, 18, 19, - } -}) -Method (CRSB, 1, Serialized) { - Name (LRTL, ResourceTemplate() { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) { 0 } - }) - CreateDWordField (LRTL, 5, LIRQ) - If (LEqual (Arg0, 8)) { - Store (16, LIRQ) - } ElseIf (LEqual (Arg0, 1)) { - Store (17, LIRQ) - } ElseIf (LEqual (Arg0, 2)) { - Store (18, LIRQ) - } ElseIf (LEqual (Arg0, 13)) { - Store (19, LIRQ) - } Else { - Store (0, LIRQ) - } - Return (LRTL) -} -Method (SRSB, 1, Serialized) { - CreateDWordField(Arg0, 5, LIRQ) - If (LEqual (LIRQ, 16)) { - Return (8) - } ElseIf (LEqual (LIRQ, 17)) { - Return (1) - } ElseIf (LEqual (LIRQ, 18)) { - Return (2) - } ElseIf (LEqual (LIRQ, 19)) { - Return (13) - } Else { - Return (0) - } -} - -/* set "C", southbridge APIC interrupts */ -Name (PRSC, ResourceTemplate () { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) { - 20, 21, 22, 23, - } -}) -Method (CRSC, 1, Serialized) { - Name (LRTL, ResourceTemplate() { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) { 0 } - }) - CreateDWordField (LRTL, 5, LIRQ) - If (LEqual (Arg0, 8)) { - Store (20, LIRQ) - } ElseIf (LEqual (Arg0, 13)) { - Store (21, LIRQ) - } ElseIf (LEqual (Arg0, 2)) { - Store (22, LIRQ) - } ElseIf (LEqual (Arg0, 1)) { - Store (23, LIRQ) - } Else { - Store (0, LIRQ) - } - Return (LRTL) -} -Method (SRSC, 1, Serialized) { - CreateDWordField(Arg0, 5, LIRQ) - If (LEqual (LIRQ, 20)) { - Return (8) - } ElseIf (LEqual (LIRQ, 21)) { - Return (13) - } ElseIf (LEqual (LIRQ, 22)) { - Return (2) - } ElseIf (LEqual (LIRQ, 23)) { - Return (1) - } Else { - Return (0) - } -} - -Device (LNKA) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 1) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTA) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTA) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSB) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSB(\_SB.PCI0.LPCB.INTA)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTA)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTA) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTA) - } - } -} -Device (LNKB) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 2) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTB) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTB) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSB) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSB(\_SB.PCI0.LPCB.INTB)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTB)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTB) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTB) - } - } -} -Device (LNKC) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 3) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTC) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTC) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSB) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSB(\_SB.PCI0.LPCB.INTC)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTC)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTC) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTC) - } - } -} -Device (LNKD) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 4) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTD) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTD) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSB) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSB(\_SB.PCI0.LPCB.INTD)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTD)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTD) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTD) - } - } -} -Device (LNKE) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 5) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTE) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTE) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSB) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSB(\_SB.PCI0.LPCB.INTE)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTE)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTE) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTE) - } - } -} -Device (LLAS) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 6) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTK) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTK) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTK)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTK)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTK) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTK) - } - } -} -Device (LUOH) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 7) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTQ) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTQ) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTQ)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTQ)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTQ) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTQ) - } - } -} -Device (LUEH) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 8) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTL) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTL) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTL)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTL)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTL) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTL) - } - } -} -Device (LAUD) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 9) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTU) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTU) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTU)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTU)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTU) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTU) - } - } -} -Device (LMOD) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 10) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTV) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTV) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTV)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTV)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTV) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTV) - } - } -} -Device (LPA0) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 11) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTW) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTW) - Store (0, \_SB.PCI0.LPCB.INTX) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTW)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTW)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), Local0) - } Else { - Store (SRSA(Arg0), Local0) - } - Store(Local0, \_SB.PCI0.LPCB.INTW) - Store(Local0, \_SB.PCI0.LPCB.INTX) - } -} -Device (LSA0) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 12) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTP) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTP) - Store (0, \_SB.PCI0.LPCB.INTG) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTP)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTP)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), Local0) - } Else { - Store (SRSA(Arg0), Local0) - } - Store(Local0, \_SB.PCI0.LPCB.INTP) - Store(Local0, \_SB.PCI0.LPCB.INTG) - } -} -Device (LSA1) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 13) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTO) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTO) - Store (0, \_SB.PCI0.LPCB.INTF) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTO)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTO)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), Local0) - } Else { - Store (SRSA(Arg0), Local0) - } - Store(Local0, \_SB.PCI0.LPCB.INTO) - Store(Local0, \_SB.PCI0.LPCB.INTF) - } -} -Device (LEMA) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 14) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTS) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTS) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTS)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTS)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTS) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTS) - } - } -} diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c deleted file mode 100644 index 3b36a69733..0000000000 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci_ops.h> -#include "ck804.h" - -static void ck804_enable_rom(void) -{ - unsigned char byte; - pci_devfn_t addr; - - /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ - /* Locate the ck804 LPC. */ - addr = PCI_DEV(0, (CK804_DEVN_BASE + 1), 0); - - /* Set the 4MB enable bit. */ - byte = pci_read_config8(addr, 0x88); - byte |= 0x80; - pci_write_config8(addr, 0x88, byte); -} - -static void bootblock_southbridge_init(void) -{ - ck804_enable_rom(); -} diff --git a/src/southbridge/nvidia/ck804/chip.h b/src/southbridge/nvidia/ck804/chip.h deleted file mode 100644 index b1676ce4ab..0000000000 --- a/src/southbridge/nvidia/ck804/chip.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOUTHBRIDGE_NVIDIA_CK804_CHIP_H -#define SOUTHBRIDGE_NVIDIA_CK804_CHIP_H - -struct southbridge_nvidia_ck804_config { - unsigned int usb1_hc_reset : 1; - unsigned int ide0_enable : 1; - unsigned int ide1_enable : 1; - unsigned int sata0_enable : 1; - unsigned int sata1_enable : 1; - unsigned int mac_eeprom_smbus; - unsigned int mac_eeprom_addr; -}; - -extern struct pci_operations ck804_pci_ops; - -#endif diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c deleted file mode 100644 index 2293392d46..0000000000 --- a/src/southbridge/nvidia/ck804/ck804.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "chip.h" - -static u32 final_reg; - -static struct device *find_lpc_dev(struct device *dev, unsigned int devfn) -{ - struct device *lpc_dev; - - lpc_dev = pcidev_path_behind(dev->bus, devfn); - if (!lpc_dev) - return lpc_dev; - - if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) - || ((lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_LPC) - && (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO) - && (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE))) - { - u32 id; - id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if ((id != (PCI_VENDOR_ID_NVIDIA | - (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16))) - && (id != (PCI_VENDOR_ID_NVIDIA | - (PCI_DEVICE_ID_NVIDIA_CK804_PRO << 16))) - && (id != (PCI_VENDOR_ID_NVIDIA | - (PCI_DEVICE_ID_NVIDIA_CK804_SLAVE << 16)))) - { - lpc_dev = 0; - } - } - - return lpc_dev; -} - -static void ck804_enable(struct device *dev) -{ - struct device *lpc_dev; - unsigned int index = 0, index2 = 0, deviceid, vendorid, devfn; - u32 reg_old, reg; - u8 byte; - - if (dev->device == 0x0000) { - vendorid = pci_read_config32(dev, PCI_VENDOR_ID); - deviceid = (vendorid >> 16) & 0xffff; - /* vendorid &= 0xffff; */ - } else { - /* vendorid = dev->vendor; */ - deviceid = dev->device; - } - - devfn = (dev->path.pci.devfn) & ~7; - switch (deviceid) { - case PCI_DEVICE_ID_NVIDIA_CK804_SM: - index = 16; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_USB: - devfn -= (1 << 3); - index = 8; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_USB2: - devfn -= (1 << 3); - index = 20; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_NIC: - devfn -= (9 << 3); - index = 10; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE: - devfn -= (9 << 3); - index = 10; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_ACI: - devfn -= (3 << 3); - index = 12; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_MCI: - devfn -= (3 << 3); - index = 13; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_IDE: - devfn -= (5 << 3); - index = 14; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_SATA0: - devfn -= (6 << 3); - index = 22; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_SATA1: - devfn -= (7 << 3); - index = 18; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_PCI: - devfn -= (8 << 3); - index = 15; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_PCI_E: - devfn -= (0xa << 3); - index2 = 19; - break; - default: - index = 0; - } - - if (index2 != 0) { - int i; - for (i = 0; i < 4; i++) { - lpc_dev = find_lpc_dev(dev, devfn - (i << 3)); - if (!lpc_dev) - continue; - index2 -= i; - break; - } - - if (lpc_dev) { - reg_old = reg = pci_read_config32(lpc_dev, 0xe4); - if (!dev->enabled) - reg |= (1 << index2); - if (reg != reg_old) - pci_write_config32(lpc_dev, 0xe4, reg); - } - - index2 = 0; - return; - } - - lpc_dev = find_lpc_dev(dev, devfn); - if (!lpc_dev) - return; - - if (index == 0) { - final_reg = pci_read_config32(lpc_dev, 0xe8); - final_reg &= ~((1 << 16) | (1 << 8) | (1 << 20) | (1 << 10) - | (1 << 12) | (1 << 13) | (1 << 14) | (1 << 22) - | (1 << 18) | (1 << 15)); - pci_write_config32(lpc_dev, 0xe8, final_reg); - - reg_old = reg = pci_read_config32(lpc_dev, 0xe4); - reg |= (1 << 20); - if (reg != reg_old) - pci_write_config32(lpc_dev, 0xe4, reg); - - byte = pci_read_config8(lpc_dev, 0x74); - byte |= ((1 << 1)); - pci_write_config8(dev, 0x74, byte); - - byte = pci_read_config8(lpc_dev, 0xdd); - byte |= ((1 << 0) | (1 << 3)); - pci_write_config8(dev, 0xdd, byte); - - return; - } - - if (!dev->enabled) - final_reg |= (1 << index); - - if (index == 10) { - reg_old = pci_read_config32(lpc_dev, 0xe8); - if (final_reg != reg_old) - pci_write_config32(lpc_dev, 0xe8, final_reg); - } -} - -static void ck804_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -struct pci_operations ck804_pci_ops = { - .set_subsystem = ck804_set_subsystem, -}; - -struct chip_operations southbridge_nvidia_ck804_ops = { - CHIP_NAME("NVIDIA CK804 Southbridge") - .enable_dev = ck804_enable, -}; diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h deleted file mode 100644 index c4c4c4f91a..0000000000 --- a/src/southbridge/nvidia/ck804/ck804.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOUTHBRIDGE_NVIDIA_CK804_CK804_H -#define SOUTHBRIDGE_NVIDIA_CK804_CK804_H - -#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE -#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE -#else -#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE -#endif - -#define CK804B_BUSN 0x80 -#define CK804B_DEVN_BASE (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) ? CK804_DEVN_BASE : 1) - -void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn); - -#endif diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c deleted file mode 100644 index bbd8210d21..0000000000 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ /dev/null @@ -1,387 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pci_ops.h> -#include <reset.h> -#include <southbridge/amd/common/reset.h> - -#include "ck804.h" - -/* Someone messed up and snuck in some K8-specific code */ -static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned int vendorid, unsigned int val) { return 0; /* stub */}; - -static int set_ht_link_ck804(u8 ht_c_num) -{ - unsigned int vendorid = 0x10de; - unsigned int val = 0x01610169; - return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); -} - -static void setup_ss_table(unsigned int index, unsigned int where, unsigned int control, - const unsigned int *register_values, int max) -{ - int i; - unsigned int val; - - val = inl(control); - val &= 0xfffffffe; - outl(val, control); - - outl(0, index); - - for (i = 0; i < max; i++) { - unsigned long reg; - reg = register_values[i]; - outl(reg, where); - } - val = inl(control); - val |= 1; - outl(val, control); -} - -#define ANACTRL_IO_BASE 0x3000 -#define ANACTRL_REG_POS 0x68 - -#define SYSCTRL_IO_BASE 0x2000 -#define SYSCTRL_REG_POS 0x64 - -/* - * Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X. - * Apparently some sort of lane configuration. - * - * 16 1 1 2 :0 - * 8 8 2 2 :1 - * 8 8 4 :2 - * 8 4 4 4 :3 - * 16 4 :4 - */ - -/* There will be implicit offsets applied, the writes below do not - * really happen at the PCI_ADDR() this expands to. - */ -#define CK804_DEV(d, f, r) PCI_ADDR(0, d, f, r) - -static void ck804_early_set_port(unsigned int ck804_num, unsigned int *busn, - unsigned int *io_base) -{ - static const unsigned int ctrl_devport_conf[] = { - CK804_DEV(0x1, 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, - CK804_DEV(0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, - }; - - int j; - for (j = 0; j < ck804_num; j++) { - u32 dev; - if (busn[j] == 0) /* SB chain */ - dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0); - else - dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0); - setup_resource_map_offset(ctrl_devport_conf, - ARRAY_SIZE(ctrl_devport_conf), dev, io_base[j]); - } -} - -static void ck804_early_clear_port(unsigned int ck804_num, unsigned int *busn, - unsigned int *io_base) -{ - static const unsigned int ctrl_devport_conf_clear[] = { - CK804_DEV(0x1, 0, ANACTRL_REG_POS), ~(0x0000ff01), 0, - CK804_DEV(0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff01), 0, - }; - - int j; - for (j = 0; j < ck804_num; j++) { - u32 dev; - if (busn[j] == 0) /* SB chain */ - dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0); - else - dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0); - setup_resource_map_offset(ctrl_devport_conf_clear, - ARRAY_SIZE(ctrl_devport_conf_clear), dev, io_base[j]); - } -} - -static void ck804_early_setup(unsigned int ck804_num, unsigned int *busn, - unsigned int *io_base) -{ - static const unsigned int ctrl_conf_master[] = { - RES_PCI_IO, CK804_DEV(1, 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, CK804_DEV(1, 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, CK804_DEV(1, 2, 0xa0), 0xfffff0ff, 0x00000a00, - RES_PCI_IO, CK804_DEV(1, 2, 0xac), 0xffffff00, 0x00000000, - - RES_PCI_IO, CK804_DEV(0, 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, CK804_DEV(0, 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, CK804_DEV(0, 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, CK804_DEV(0, 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, CK804_DEV(0, 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, CK804_DEV(0, 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, CK804_DEV(0, 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, CK804_DEV(0, 0, 0xdc), 0x7f000000, 0x00000000, - - RES_PCI_IO, CK804_DEV(1, 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, CK804_DEV(1, 0, 0xf8), 0xffffffcf, 0x00000010, - - RES_PCI_IO, CK804_DEV(9, 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, CK804_DEV(9, 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, CK804_DEV(9, 0, 0x74), 0xffffffc0, 0x00000000, - -#ifdef CK804_MB_SETUP - CK804_MB_SETUP -#endif - -#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) - /* - * Avoid crash (complete with severe memory corruption!) during initial CAR boot - * in ck804_early_setup_x() on Fam10h systems by not touching 0x78. - * Interestingly once the system is fully booted into Linux this can be set, but - * not before! Apparently something isn't initialized but the amount of effort - * required to fix this is non-negligible and of unknown real-world benefit - */ -#else - RES_PCI_IO, CK804_DEV(1, 0, 0x78), 0xc0ffffff, 0x19000000, -#endif - RES_PCI_IO, CK804_DEV(1, 0, 0xe0), 0xfffffeff, 0x00000100, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32), - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16), - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, - - /* Activate master port on primary SATA controller. */ - RES_PCI_IO, CK804_DEV(7, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, CK804_DEV(7, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, CK804_DEV(7, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, CK804_DEV(7, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, CK804_DEV(7, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, CK804_DEV(7, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, CK804_DEV(7, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, CK804_DEV(7, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, CK804_DEV(7, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, CK804_DEV(7, 0, 0xe0), ~(0xf0000000), 0x00000000, - - RES_PCI_IO, CK804_DEV(8, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, CK804_DEV(8, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, CK804_DEV(8, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, CK804_DEV(8, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, CK804_DEV(8, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, CK804_DEV(8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, CK804_DEV(8, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, CK804_DEV(8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, CK804_DEV(8, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, CK804_DEV(8, 0, 0xe0), ~(0xf0000000), 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8), - - /* SYSCTRL */ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), -#if CONFIG(CK804_USE_NIC) - RES_PCI_IO, CK804_DEV(0xa, 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), - RES_PCI_IO, CK804_DEV(1, 0, 0xe4), ~(1 << 23), (1 << 23), -#endif - -#if CONFIG(CK804_USE_ACI) - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), -#endif - -#if CONFIG(CK804_PCIE_PME_WAKE) - RES_PCI_IO, CK804_DEV(1, 0, 0xe4), 0xffffffff, 0x00400000, -#else - RES_PCI_IO, CK804_DEV(1, 0, 0xe4), 0xffbfffff, 0x00000000, -#endif - }; - - static const unsigned int ctrl_conf_multiple[] = { - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2), - }; - - static const unsigned int ctrl_conf_slave[] = { - RES_PCI_IO, CK804_DEV(1, 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, CK804_DEV(1, 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, CK804_DEV(1, 2, 0xa0), 0xfffff0ff, 0x00000a00, - - RES_PCI_IO, CK804_DEV(0, 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, CK804_DEV(0, 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, CK804_DEV(0, 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, CK804_DEV(0, 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, CK804_DEV(0, 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, CK804_DEV(0, 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, CK804_DEV(0, 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, CK804_DEV(0, 0, 0xdc), 0x7f000000, 0x00000000, - - RES_PCI_IO, CK804_DEV(1, 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, CK804_DEV(1, 0, 0xf8), 0xffffffcf, 0x00000010, - - RES_PCI_IO, CK804_DEV(9, 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, CK804_DEV(9, 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, CK804_DEV(9, 0, 0x74), 0xffffffc0, 0x00000000, - - /* - * Avoid touching 0x78 for CONFIG_NORTHBRIDGE_AMD_AMDFAM10 for - * non-primary chains too??? - */ - RES_PCI_IO, CK804_DEV(1, 0, 0x78), 0xc0ffffff, 0x20000000, - RES_PCI_IO, CK804_DEV(1, 0, 0xe0), 0xfffffeff, 0x00000000, - RES_PCI_IO, CK804_DEV(1, 0, 0xe8), 0xffffff00, 0x000000ff, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, - - RES_PCI_IO, CK804_DEV(8, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, CK804_DEV(8, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, CK804_DEV(8, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, CK804_DEV(8, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, CK804_DEV(8, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, CK804_DEV(8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, CK804_DEV(8, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, CK804_DEV(8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, CK804_DEV(8, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, CK804_DEV(8, 0, 0xe0), ~(0xf0000000), 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, - - /* This line doesn't exist in the non-CAR version. */ - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8), - -#if CONFIG(CK804_USE_NIC) - RES_PCI_IO, CK804_DEV(0xa, 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), - RES_PCI_IO, CK804_DEV(1, 0, 0xe4), ~(1 << 23), (1 << 23), -#endif - }; - - int j; - for (j = 0; j < ck804_num; j++) { - if (busn[j] == 0) { - setup_resource_map_x_offset(ctrl_conf_master, - ARRAY_SIZE(ctrl_conf_master), - PCI_DEV(0, CK804_DEVN_BASE, 0), io_base[0]); - if (ck804_num > 1) - setup_resource_map_x_offset(ctrl_conf_multiple, - ARRAY_SIZE(ctrl_conf_multiple), - PCI_DEV(0, CK804_DEVN_BASE, 0), 0); - - continue; - } - - setup_resource_map_x_offset(ctrl_conf_slave, - ARRAY_SIZE(ctrl_conf_slave), - PCI_DEV(busn[j], CK804B_DEVN_BASE, 0), io_base[j]); - } - - for (j = 0; j < ck804_num; j++) { - /* PCI-E (XSPLL) SS table 0x40, x044, 0x48 */ - /* SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 */ - /* CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 */ - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40, - io_base[j] + ANACTRL_IO_BASE + 0x44, - io_base[j] + ANACTRL_IO_BASE + 0x48, - pcie_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0, - io_base[j] + ANACTRL_IO_BASE + 0xb4, - io_base[j] + ANACTRL_IO_BASE + 0xb8, - sata_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, - io_base[j] + ANACTRL_IO_BASE + 0xc4, - io_base[j] + ANACTRL_IO_BASE + 0xc8, - cpu_ss_tbl, 64); - } -} - -static int ck804_early_setup_x(void) -{ - unsigned int busn[4], io_base[4]; - int i, ck804_num = 0; - - for (i = 0; i < 4; i++) { - u32 id; - pci_devfn_t dev; - if (i == 0) /* SB chain */ - dev = PCI_DEV(i * 0x40, CK804_DEVN_BASE, 0); - else - dev = PCI_DEV(i * 0x40, CK804B_DEVN_BASE, 0); - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (id == 0x005e10de) { - busn[ck804_num] = i * 0x40; - io_base[ck804_num] = i * 0x4000; - ck804_num++; - } - } - - ck804_early_set_port(ck804_num, busn, io_base); - ck804_early_setup(ck804_num, busn, io_base); - ck804_early_clear_port(ck804_num, busn, io_base); - - return set_ht_link_ck804(4); -} - -void do_board_reset(void) -{ - set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -void do_soft_reset(void) -{ - set_bios_reset(); - - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -} - -void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn) -{ - /* The default value for CK804 is good. */ - /* Set VFSMAF (VID/FID System Management Action Field) to 2. */ -} diff --git a/src/southbridge/nvidia/ck804/early_setup_ss.h b/src/southbridge/nvidia/ck804/early_setup_ss.h deleted file mode 100644 index 69220d9549..0000000000 --- a/src/southbridge/nvidia/ck804/early_setup_ss.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -static const unsigned int pcie_ss_tbl[] = { - 0x0C504103f, - 0x0C504103f, - 0x0C504103f, - 0x0C5042040, - 0x0C5042040, - 0x0C5042040, - 0x0C5043041, - 0x0C5043041, - 0x0C5043041, - 0x0C5043041, - 0x0C5044042, - 0x0C5044042, - 0x0C5044042, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5048046, - 0x0C5048046, - 0x0C5048046, - 0x0C5048046, - 0x0C5049047, - 0x0C5049047, - 0x0C5049047, - 0x0C504a048, - 0x0C504a048, - 0x0C504b049, - 0x0C504b049, - 0x0C504a048, - 0x0C504a048, - 0x0C5049047, - 0x0C5049047, - 0x0C5048046, - 0x0C5048046, - 0x0C5048046, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5044042, - 0x0C5044042, - 0x0C5044042, - 0x0C5043041, - 0x0C5043041, - 0x0C5042040, - 0x0C5042040, -}; - -static const unsigned int sata_ss_tbl[] = { - 0x0c9044042, - 0x0c9044042, - 0x0c9044042, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9044042, - 0x0c9044042, - 0x0c9044042, -}; - -static const unsigned int cpu_ss_tbl[] = { - 0x0C5038036, - 0x0C5038036, - 0x0C5038036, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5038036, - 0x0C5038036, - 0x0C5038036, - 0x0C5038036, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503b039, - 0x0C503b039, - 0x0C503b039, - 0x0C503b039, - 0x0C503b039, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, -}; diff --git a/src/southbridge/nvidia/ck804/early_smbus.c b/src/southbridge/nvidia/ck804/early_smbus.c deleted file mode 100644 index 8997ef0da6..0000000000 --- a/src/southbridge/nvidia/ck804/early_smbus.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <device/pci.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> - -#include "smbus.h" -#include "early_smbus.h" - -#define SMBUS_BAR_BASE 0x20 -#define SMBUS_IO_BASE 0x1000 -#define SMBUS_IO_SIZE 0x0040 - -#define SMBUS_BAR(x) (SMBUS_BAR_BASE + 4 * (x)) -#define SMBUS_BASE(x) (SMBUS_IO_BASE + SMBUS_IO_SIZE * (x)) - -void enable_smbus(void) -{ - pci_devfn_t dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_NVIDIA, - PCI_DEVICE_ID_NVIDIA_CK804_SMB), 0); - if (dev == PCI_DEV_INVALID) - die("SMBus controller not found\n"); - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMBUS_BAR(0), SMBUS_BASE(0) | 1); - pci_write_config32(dev, SMBUS_BAR(1), SMBUS_BASE(1) | 1); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, 0x4, 0x01); - - /* Clear any lingering errors, so the transaction will run. */ - outb(inb(SMBUS_BASE(0) + SMBHSTSTAT), SMBUS_BASE(0) + SMBHSTSTAT); - outb(inb(SMBUS_BASE(1) + SMBHSTSTAT), SMBUS_BASE(1) + SMBHSTSTAT); - - printk(BIOS_DEBUG, "SMBus controller enabled\n"); -} - -int ck804_smbus_read_byte(unsigned int bus, unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_BASE(bus), device, address); -} - -int ck804_smbus_write_byte(unsigned int bus, unsigned int device, unsigned int address, - unsigned char val) -{ - return do_smbus_write_byte(SMBUS_BASE(bus), device, address, val); -} - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return ck804_smbus_read_byte(0, device, address); -} - -int smbus_write_byte(unsigned int device, unsigned int address, unsigned char val) -{ - return ck804_smbus_write_byte(0, device, address, val); -} diff --git a/src/southbridge/nvidia/ck804/early_smbus.h b/src/southbridge/nvidia/ck804/early_smbus.h deleted file mode 100644 index 30c4b02fa5..0000000000 --- a/src/southbridge/nvidia/ck804/early_smbus.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -int ck804_smbus_read_byte(unsigned int, unsigned int, unsigned int); -int ck804_smbus_write_byte(unsigned int, unsigned int, unsigned int, unsigned char); -void enable_smbus(void); -int smbus_read_byte(unsigned int, unsigned int); -int smbus_write_byte(unsigned int, unsigned int, unsigned char); diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c deleted file mode 100644 index e8315092d6..0000000000 --- a/src/southbridge/nvidia/ck804/enable_usbdebug.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include <stdint.h> -#include <device/pci_ops.h> -#include <device/pci_ehci.h> -#include <device/pci_def.h> -#include "ck804.h" - -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) -{ - return PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ -} - -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) -{ - u32 dword; - - /* Write the port number to 0x74[15:12]. */ - dword = pci_read_config32(dev, 0x74); - dword &= ~(0xf << 12); - dword |= (port << 12); - pci_write_config32(dev, 0x74, dword); -} diff --git a/src/southbridge/nvidia/ck804/fadt.c b/src/southbridge/nvidia/ck804/fadt.c deleted file mode 100644 index 55f98bffce..0000000000 --- a/src/southbridge/nvidia/ck804/fadt.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * (C) Copyright 2005 Stefan Reinauer <stepan@openbios.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * ACPI - create the Fixed ACPI Description Tables (FADT) - */ - -#include <string.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <version.h> - -extern unsigned int pm_base; /* pm_base should be set in sb acpi */ - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); - - /* Prepare the header */ - memset((void *)fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = get_acpi_table_revision(FADT); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = asl_revision; - - fadt->firmware_ctrl = (u32)facs; - fadt->dsdt = (u32)dsdt; - // 3=Workstation,4=Enterprise Server, 7=Performance Server - fadt->preferred_pm_profile = 0; - fadt->sci_int = 9; - // disable system management mode by setting to 0: - fadt->smi_cmd = 0; - fadt->acpi_enable = 0; - fadt->acpi_disable = 0; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0x0; - - fadt->pm1a_evt_blk = pm_base; - fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = pm_base + 0x04; - fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = pm_base + 0x1c; - fadt->pm_tmr_blk = pm_base + 0x08; - fadt->gpe0_blk = pm_base + 0x20; - fadt->gpe1_blk = 0x0000; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 0xffff; - fadt->p_lvl3_lat = 0xffff; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0x7d; - fadt->mon_alrm = 0x7e; - fadt->century = 0x32; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; - fadt->flags = 0xa5; - -#ifdef LONG_FADT - fadt->res2 = 0; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; - fadt->x_pm1a_evt_blk.addrl = pm_base; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 4; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; - fadt->x_pm1a_cnt_blk.addrl = pm_base + 4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 2; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; - fadt->x_pm2_cnt_blk.addrl = 0x0; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; - fadt->x_pm_tmr_blk.addrl = pm_base + 0x08; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 32; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; - fadt->x_gpe0_blk.addrl = pm_base + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 64; - fadt->x_gpe1_blk.bit_offset = 16; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = pm_base + 0xb0; - fadt->x_gpe1_blk.addrh = 0x0; -#endif - header->checksum = acpi_checksum((void *)fadt, header->length); -} diff --git a/src/southbridge/nvidia/ck804/ht.c b/src/southbridge/nvidia/ck804/ht.c deleted file mode 100644 index 2925b05068..0000000000 --- a/src/southbridge/nvidia/ck804/ht.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <arch/acpi.h> -#include "chip.h" - -#if CONFIG(HAVE_ACPI_TABLES) - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - struct device *dev; - unsigned long mcfg_base; - - dev = pcidev_on_root(0x0, 0); - if (!dev) - return current; - - mcfg_base = pci_read_config16(dev, 0x90); - if ((mcfg_base & 0x1000) == 0) - return current; - - mcfg_base = (mcfg_base & 0xf) << 28; - - printk(BIOS_INFO, "mcfg_base %lx.\n", mcfg_base); - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, mcfg_base, 0x0, 0x0, 0xff); - return current; -} - -#endif - -static void ht_init(struct device *dev) -{ - u32 htmsi; - - /* Enable HT MSI Mapping in capability register */ - htmsi = pci_read_config32(dev, 0xe0); - htmsi |= (1 << 16); - pci_write_config32(dev, 0xe0, htmsi); -} - -static struct device_operations ht_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ht_init, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver ht_driver __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_HT, -}; diff --git a/src/southbridge/nvidia/ck804/ide.c b/src/southbridge/nvidia/ck804/ide.c deleted file mode 100644 index a4b5475ca0..0000000000 --- a/src/southbridge/nvidia/ck804/ide.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "chip.h" - -static void ide_init(struct device *dev) -{ - struct southbridge_nvidia_ck804_config *conf; - u32 dword; - u16 word; - u8 byte; - - conf = dev->chip_info; - - word = pci_read_config16(dev, 0x50); - /* Ensure prefetch is disabled. */ - word &= ~((1 << 15) | (1 << 13)); - if (conf->ide1_enable) { - /* Enable secondary IDE interface. */ - word |= (1 << 0); - printk(BIOS_DEBUG, "IDE1\t"); - } - if (conf->ide0_enable) { - /* Enable primary IDE interface. */ - word |= (1 << 1); - printk(BIOS_DEBUG, "IDE0\n"); - } - - word |= (1 << 12); - word |= (1 << 14); - - pci_write_config16(dev, 0x50, word); - - byte = 0x20; /* Latency: 64 --> 32 */ - pci_write_config8(dev, 0xd, byte); - - dword = pci_read_config32(dev, 0xf8); - dword |= 12; - pci_write_config32(dev, 0xf8, dword); -} - -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_IDE, -}; diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c deleted file mode 100644 index b8aec2667d..0000000000 --- a/src/southbridge/nvidia/ck804/lpc.c +++ /dev/null @@ -1,348 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering - * Copyright (C) 2003 Linux Networx - * Copyright (C) 2003 SuSE Linux AG - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pnp.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <pc80/mc146818rtc.h> -#include <pc80/isa-dma.h> -#include <arch/io.h> -#include <arch/ioapic.h> -#include <arch/acpi.h> -#include <cpu/x86/lapic.h> -#include <stdlib.h> -#include <assert.h> -#include <cpu/amd/powernow.h> -#include "chip.h" - -#define NMI_OFF 0 - -// Power restoration control register is at 0x7a -#define PREVIOUS_POWER_STATE 0x7A - - // Auxiliary power control register possibly located at 0xe3 -#define PREVIOUS_POWER_STATE_AUX 0xe3 - -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 -#define SLOW_CPU_OFF 0 -#define SLOW_CPU__ON 1 - -static void lpc_common_init(struct device *dev) -{ - u32 dword; - struct resource *res; - - /* I/O APIC initialization. */ - res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */ - ASSERT(res != NULL); - setup_ioapic(res2mmio(res, 0, 0), 0); /* Don't rename IOAPIC ID. */ - -#if 1 - dword = pci_read_config32(dev, 0xe4); - dword |= (1 << 23); - pci_write_config32(dev, 0xe4, dword); -#endif -} - -static void lpc_slave_init(struct device *dev) -{ - lpc_common_init(dev); -} - -static void rom_dummy_write(struct device *dev) -{ - u8 old, new; - u8 *p; - - old = pci_read_config8(dev, 0x88); - new = old | 0xc0; - if (new != old) - pci_write_config8(dev, 0x88, new); - /* Enable write. */ - old = pci_read_config8(dev, 0x6d); - new = old | 0x01; - if (new != old) - pci_write_config8(dev, 0x6d, new); - - /* Dummy write. */ - p = (u8 *) 0xffffffe0; - old = 0; - *p = old; - old = *p; - - /* Disable write. */ - old = pci_read_config8(dev, 0x6d); - new = old & 0xfe; - if (new != old) - pci_write_config8(dev, 0x6d, new); -} - -unsigned int pm_base = 0; - -static void lpc_init(struct device *dev) -{ - u8 byte, byte_old; - int on, nmi_option; - - lpc_common_init(dev); - - pm_base = pci_read_config32(dev, 0x60) & 0xff00; - printk(BIOS_INFO, "%s: pm_base = %x\n", __func__, pm_base); - - /* Power after power fail */ - on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - get_option(&on, "power_on_after_fail"); - byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); - byte &= ~0x45; - if (!on) - byte |= 0x45; - pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); - printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off"); - - /* Throttle the CPU speed down for testing. */ - on = SLOW_CPU_OFF; - get_option(&on, "slow_cpu"); - if (on) { - u16 pm10_bar; - pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00); - outl(((on << 1) + 0x10), (pm10_bar + 0x10)); - inl(pm10_bar + 0x10); - on = 8 - on; - printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", - (on * 12) + (on >> 1), (on & 1) * 5); - } - - /* Set up NMI on errors. */ - byte = inb(0x70); /* RTC70 */ - byte_old = byte; - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) - byte &= ~(1 << 7); /* Set NMI. */ - else - byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */ - if (byte != byte_old) - outb(byte, 0x70); - - /* Initialize the real time clock (RTC). */ - cmos_init(0); - - /* Initialize ISA DMA. */ - isa_dma_init(); - - rom_dummy_write(dev); -} - -static void ck804_lpc_read_resources(struct device *dev) -{ - struct resource *res; - unsigned long index; - - /* Get the normal PCI resources of this device. */ - /* We got one for APIC, or one more for TRAP. */ - pci_dev_read_resources(dev); - - /* HPET */ - pci_get_resource(dev, 0x44); - - /* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */ - for (index = 0x60; index <= 0x68; index += 4) /* We got another 3. */ - pci_get_resource(dev, index); - compact_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - if (dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE) { - res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */ - if (res) { - res->base = IO_APIC_ADDR; - res->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } - - res = find_resource(dev, 0x44); /* HPET */ - if (res) { - res->base = CONFIG_HPET_ADDRESS; - res->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } - } -} - -static void ck804_lpc_set_resources(struct device *dev) -{ - u8 byte; - struct resource *res; - - pci_dev_set_resources(dev); - - /* APIC */ - res = find_resource(dev, PCI_BASE_ADDRESS_1); - if (res) { - byte = pci_read_config8(dev, 0x74); - byte |= (1 << 1); /* enable access to PCI_BASE_ADDRESS_1 */ - pci_write_config8(dev, 0x74, byte); - pci_write_config32(dev, PCI_BASE_ADDRESS_1, res->base); - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - byte |= (1 << 0); /* enable decode of IOAPIC space */ - byte &= ~(1 << 1); /* hide PCI_BASE_ADDRESS_1 */ - pci_write_config8(dev, 0x74, byte); - } - - /* HPET */ - res = find_resource(dev, 0x44); - if (res) { - pci_write_config32(dev, 0x44, res->base|1); - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -} - -/** - * Enable resources for children devices. - * - * This function is called by the global enable_resources() indirectly via the - * device_operation::enable_resources() method of devices. - */ -static void ck804_lpc_enable_childrens_resources(struct device *dev) -{ - struct bus *link; - u32 reg, reg_var[4]; - int i, var_num = 0; - - reg = pci_read_config32(dev, 0xa0); - - for (link = dev->link_list; link; link = link->next) { - struct device *child; - for (child = link->children; child; child = child->sibling) { - if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { - struct resource *res; - for (res = child->resource_list; res; res = res->next) { - unsigned long base, end; /* Don't need long long. */ - if (!(res->flags & IORESOURCE_IO)) - continue; - base = res->base; - end = resource_end(res); - printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\n", dev_path(child), base, end); - switch (base) { - case 0x3f8: // COM1 - reg |= (1 << 0); - break; - case 0x2f8: // COM2 - reg |= (1 << 1); - break; - case 0x378: // Parallel 1 - reg |= (1 << 24); - break; - case 0x3f0: // FD0 - reg |= (1 << 20); - break; - case 0x220: // Audio 0 - reg |= (1 << 8); - break; - case 0x300: // Midi 0 - reg |= (1 << 12); - break; - } - if (base == 0x290 || base >= 0x400) { - /* Only 4 var; compact them? */ - if (var_num >= 4) - continue; - reg |= (1 << (28 + var_num)); - reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16); - } - } - } - } - } - pci_write_config32(dev, 0xa0, reg); - for (i = 0; i < var_num; i++) - pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); -} - -static void ck804_lpc_enable_resources(struct device *dev) -{ - pci_dev_enable_resources(dev); - ck804_lpc_enable_childrens_resources(dev); -} - -#if CONFIG(HAVE_ACPI_TABLES) - -static void southbridge_acpi_fill_ssdt_generator(struct device *device) -{ - amd_generate_powernow(0, 0, 0); -} - -#endif - -static struct device_operations lpc_ops = { - .read_resources = ck804_lpc_read_resources, - .set_resources = ck804_lpc_set_resources, - .enable_resources = ck804_lpc_enable_resources, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, - .write_acpi_tables = acpi_write_hpet, -#endif - .init = lpc_init, - .scan_bus = scan_static_bus, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_LPC, -}; - -static const struct pci_driver lpc_driver_pro __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_PRO, -}; - -static struct device_operations lpc_slave_ops = { - .read_resources = ck804_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = acpi_write_hpet, -#endif - .init = lpc_slave_init, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver lpc_driver_slave __pci_driver = { - .ops = &lpc_slave_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE, -}; diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c deleted file mode 100644 index 5dbb6b4aa9..0000000000 --- a/src/southbridge/nvidia/ck804/nic.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/smbus.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/mmio.h> -#include "chip.h" - -static void nic_init(struct device *dev) -{ - u32 dword, old, mac_h = 0, mac_l = 0; - int eeprom_valid = 0; - struct southbridge_nvidia_ck804_config *conf; - static u32 nic_index = 0; - u8 *base; - struct resource *res; - - res = find_resource(dev, 0x10); - base = res2mmio(res, 0, 0); - -#define NvRegPhyInterface 0xC0 -#define PHY_RGMII 0x10000000 - - write32(base + NvRegPhyInterface, PHY_RGMII); - - old = dword = pci_read_config32(dev, 0x30); - dword &= ~(0xf); - dword |= 0xf; - if (old != dword) - pci_write_config32(dev, 0x30, dword); - - conf = dev->chip_info; - - if (conf->mac_eeprom_smbus != 0) { - /* Read MAC address from EEPROM at first. */ - struct device *dev_eeprom; - dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, - conf->mac_eeprom_addr); - - if (dev_eeprom) { - /* If that is valid we will use that. */ - unsigned char dat[6]; - int i, status; - for (i = 0; i < 6; i++) { - status = smbus_read_byte(dev_eeprom, i); - if (status < 0) - break; - dat[i] = status & 0xff; - } - if (status >= 0) { - mac_l = 0; - for (i = 3; i >= 0; i--) { - mac_l <<= 8; - mac_l += dat[i]; - } - if (mac_l != 0xffffffff) { - mac_l += nic_index; - mac_h = 0; - for (i = 5; i >= 4; i--) { - mac_h <<= 8; - mac_h += dat[i]; - } - eeprom_valid = 1; - } - } - } - } - - /* If that is invalid we will read that from romstrap. */ - if (!eeprom_valid) { - u32 *mac_pos; - mac_pos = (u32 *)0xffffffd0; /* See romstrap.inc and romstrap.ld. */ - mac_l = read32(mac_pos) + nic_index; - mac_h = read32(mac_pos + 1); - } -#if 1 - /* Set that into NIC MMIO. */ -#define NvRegMacAddrA 0xA8 -#define NvRegMacAddrB 0xAC - write32(base + NvRegMacAddrA, mac_l); - write32(base + NvRegMacAddrB, mac_h); -#else - /* Set that into NIC. */ - pci_write_config32(dev, 0xa8, mac_l); - pci_write_config32(dev, 0xac, mac_h); -#endif - - nic_index++; -} - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver nic_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC, -}; - -static const struct pci_driver nic_bridge_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE, -}; diff --git a/src/southbridge/nvidia/ck804/pci.c b/src/southbridge/nvidia/ck804/pci.c deleted file mode 100644 index d4b074d14b..0000000000 --- a/src/southbridge/nvidia/ck804/pci.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/resource.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "chip.h" - -static void pci_init(struct device *dev) -{ - u32 dword; - struct device *pci_domain_dev; - struct resource *mem, *pref; - - dword = pci_read_config32(dev, 0x04); - dword |= (1 << 8); /* System error enable */ - dword |= (1 << 30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); - - dword = pci_read_config32(dev, 0x4c); - dword |= 0x00440000; /* TABORT_SER_ENABLE Park Last Enable. */ - pci_write_config32(dev, 0x4c, dword); - - pci_domain_dev = dev->bus->dev; - while (pci_domain_dev) { - if (pci_domain_dev->path.type == DEVICE_PATH_DOMAIN) - break; - pci_domain_dev = pci_domain_dev->bus->dev; - } - - if (!pci_domain_dev) - return; /* Impossible */ - - pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0)); - mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0)); - - if (!mem) - return; /* Impossible */ - - if (!pref || pref->base > mem->base) { - dword = mem->base & (0xffff0000UL); - printk(BIOS_DEBUG, "PCI DOMAIN mem base = 0x%010Lx\n", mem->base); - } else { - dword = pref->base & (0xffff0000UL); - printk(BIOS_DEBUG, "PCI DOMAIN pref base = 0x%010Lx\n", pref->base); - } - - printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword); - pci_write_config32(dev, 0x50, dword); /* TOM */ -} - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI, -}; diff --git a/src/southbridge/nvidia/ck804/pcie.c b/src/southbridge/nvidia/ck804/pcie.c deleted file mode 100644 index 7bd8324d8c..0000000000 --- a/src/southbridge/nvidia/ck804/pcie.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "chip.h" - -static void pcie_init(struct device *dev) -{ - u32 dword; - - /* Enable PCI error detecting. */ - dword = pci_read_config32(dev, 0x04); - dword |= (1 << 8); /* System error enable */ - dword |= (1 << 30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); -} - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, -}; - -static const struct pci_driver pcie_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI_E, -}; diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c deleted file mode 100644 index f828c53e71..0000000000 --- a/src/southbridge/nvidia/ck804/reset.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include <arch/io.h> -#include <reset.h> - -#include "../../../northbridge/amd/amdk8/reset_test.c" - -void do_board_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9. */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} diff --git a/src/southbridge/nvidia/ck804/romstrap.S b/src/southbridge/nvidia/ck804/romstrap.S deleted file mode 100644 index 5a20107376..0000000000 --- a/src/southbridge/nvidia/ck804/romstrap.S +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - .section ".romstrap", "a", @progbits - - - .align 16 - .globl __romstrap_start -__romstrap_start: -rstables: - .long 0x2b16d065 - .long 0x0 - .long 0x0 - .long linkedlist - -linkedlist: - .long 0x0003001C // 10h - .long 0x08000000 // 14h - .long 0x00000000 // 18h - .long 0xFFFFFFFF // 1Ch - - .long 0xFFFFFFFF // 20h - .long 0xFFFFFFFF // 24h - .long 0xFFFFFFFF // 28h - .long 0xFFFFFFFF // 2Ch - - .long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0 - .long 0x000000E0 // 34h, MAC address high 4 byte - - .long 0x002309CE // 38h, UUID low 4 byte - .long 0x00E08100 // 3Ch, UUID high 4 byte - -rspointers: - .long rstables // It will be 0xffffffe0 - .long rstables - .long rstables - .long rstables - - .globl __romstrap_end - -__romstrap_end: -.previous diff --git a/src/southbridge/nvidia/ck804/romstrap.ld b/src/southbridge/nvidia/ck804/romstrap.ld deleted file mode 100644 index 6b14be9d8a..0000000000 --- a/src/southbridge/nvidia/ck804/romstrap.ld +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -SECTIONS { - . = (0xffffffff - 0x10) - (__romstrap_end - __romstrap_start) + 1; - .romstrap (.): { - KEEP(*(.romstrap)) - } -} diff --git a/src/southbridge/nvidia/ck804/sata.c b/src/southbridge/nvidia/ck804/sata.c deleted file mode 100644 index 9abd6d26ba..0000000000 --- a/src/southbridge/nvidia/ck804/sata.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <delay.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "chip.h" - -#ifndef CK804_SATA_RESET_FOR_ATAPI -#define CK804_SATA_RESET_FOR_ATAPI 0 -#endif - -#if CK804_SATA_RESET_FOR_ATAPI -static void sata_com_reset(struct device *dev, unsigned int reset) -// reset = 1 : reset -// reset = 0 : clear -{ - u32 *base; - u32 dword; - int loop; - - base = (u32 *) pci_read_config32(dev, 0x24); - - printk(BIOS_DEBUG, "base = %08lx\n", base); - - if (reset) { - *(base + 4) = 0xffffffff; - *(base + 0x44) = 0xffffffff; - } - - dword = *(base + 8); - dword &= ~(0xf); - dword |= reset; - - *(base + 8) = dword; - *(base + 0x48) = dword; - - if (reset) - return; - - dword = *(base + 0); - printk(BIOS_DEBUG, "*(base+0)=%08x\n", dword); - if (dword == 0x113) { - loop = 200000; // 2 - do { - dword = *(base + 4); - if ((dword & 0x10000) != 0) - break; - udelay(10); - } while (--loop > 0); - printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\n", loop, dword); - } - - dword = *(base + 0x40); - printk(BIOS_DEBUG, "*(base+0x40)=%08x\n", dword); - if (dword == 0x113) { - loop = 200000; //2 - do { - dword = *(base + 0x44); - if ((dword & 0x10000) != 0) - break; - udelay(10); - } while (--loop > 0); - printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\n", loop, dword); - } -} -#endif - -static void sata_init(struct device *dev) -{ - u32 dword; - struct southbridge_nvidia_ck804_config *conf; - - conf = dev->chip_info; - - dword = pci_read_config32(dev, 0x50); - /* Ensure prefetch is disabled. */ - dword &= ~((1 << 15) | (1 << 13)); - if (conf->sata1_enable) { - /* Enable secondary SATA interface. */ - dword |= (1 << 0); - printk(BIOS_DEBUG, "SATA S\t"); - } - if (conf->sata0_enable) { - /* Enable primary SATA interface. */ - dword |= (1 << 1); - printk(BIOS_DEBUG, "SATA P\n"); - } - -#if 1 - /* DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. */ - dword &= ~(0x1f << 24); - dword |= (0x15 << 24); -#endif - pci_write_config32(dev, 0x50, dword); - - dword = pci_read_config32(dev, 0xf8); - dword |= 2; - pci_write_config32(dev, 0xf8, dword); - -#if CK804_SATA_RESET_FOR_ATAPI - dword = pci_read_config32(dev, 0xac); - dword &= ~((1 << 13) | (1 << 14)); - dword |= (1 << 13) | (0 << 14); - pci_write_config32(dev, 0xac, dword); - - sata_com_reset(dev, 1); /* For discover some s-atapi device. */ -#endif -} - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_SATA0, -}; - -static const struct pci_driver sata1_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_SATA1, -}; diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c deleted file mode 100644 index 9737d0070f..0000000000 --- a/src/southbridge/nvidia/ck804/smbus.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/smbus.h> -#include "chip.h" -#include "smbus.h" - -static int lsmbus_recv_byte(struct device *dev) -{ - unsigned int device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); - - return do_smbus_recv_byte(res->base, device); -} - -static int lsmbus_send_byte(struct device *dev, u8 val) -{ - unsigned int device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); - - return do_smbus_send_byte(res->base, device, val); -} - -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - unsigned int device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) -{ - unsigned int device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); - - return do_smbus_write_byte(res->base, device, address, val); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .recv_byte = lsmbus_recv_byte, - .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static struct device_operations smbus_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_smbus, - .ops_pci = &ck804_pci_ops, - .ops_smbus_bus = &lops_smbus_bus, -}; - -static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_SM, -}; diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h deleted file mode 100644 index 9aad5e14f0..0000000000 --- a/src/southbridge/nvidia/ck804/smbus.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/smbus_def.h> - -#define SMBHSTSTAT 0x1 -#define SMBHSTPRTCL 0x0 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x2 -#define SMBHSTDAT0 0x4 -#define SMBHSTDAT1 0x5 - -/* - * Between 1-10 seconds, We should never timeout normally. - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100 * 1000 * 10) - -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_done(unsigned int smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(smbus_io_base + SMBHSTSTAT); - if ((val & 0xff) != 0) - return 0; - } while (--loops); - return -3; -} - - -/* Platform has severe issues placing non-inlined functions in headers. */ -#if ENV_RAMSTAGE -static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device) -{ - unsigned char global_status_register, byte; - - /* Set the device I'm talking to. */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); - smbus_delay(); - - /* Set the command/address. */ - outb(0, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* Byte data recv. */ - outb(0x05, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* Poll for transaction completion. */ - if (smbus_wait_until_done(smbus_io_base) < 0) - return -3; - - /* Lose check. */ - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; - - /* Read results of transaction. */ - byte = inb(smbus_io_base + SMBHSTDAT0); - - /* Lose check, otherwise it should be 0. */ - if (global_status_register != 0x80) - return -1; - - return byte; -} - -static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device, - unsigned char val) -{ - unsigned int global_status_register; - - outb(val, smbus_io_base + SMBHSTDAT0); - smbus_delay(); - - /* Set the device I'm talking to. */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); - smbus_delay(); - - outb(0, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* Set up for a byte data write. */ - outb(0x04, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* Poll for transaction completion. */ - if (smbus_wait_until_done(smbus_io_base) < 0) - return -3; - - /* Lose check. */ - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; - - if (global_status_register != 0x80) - return -1; - - return 0; -} -#endif /* ENV_RAMSTAGE */ - -static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device, - unsigned int address) -{ - unsigned char global_status_register, byte; - - /* Set the device I'm talking to. */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); - smbus_delay(); - - /* Set the command/address. */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* Byte data read. */ - outb(0x07, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* Poll for transaction completion. */ - if (smbus_wait_until_done(smbus_io_base) < 0) - return -3; - - /* Lose check. */ - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; - - /* Read results of transaction. */ - byte = inb(smbus_io_base + SMBHSTDAT0); - - /* Lose check, otherwise it should be 0. */ - if (global_status_register != 0x80) - return -1; - - return byte; -} - -static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device, - unsigned int address, unsigned char val) -{ - unsigned int global_status_register; - - outb(val, smbus_io_base + SMBHSTDAT0); - smbus_delay(); - - /* Set the device I'm talking to. */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); - smbus_delay(); - - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* Set up for a byte data write. */ - outb(0x06, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* Poll for transaction completion. */ - if (smbus_wait_until_done(smbus_io_base) < 0) - return -3; - - /* Lose check. */ - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; - - if (global_status_register != 0x80) - return -1; - - return 0; -} diff --git a/src/southbridge/nvidia/ck804/usb.c b/src/southbridge/nvidia/ck804/usb.c deleted file mode 100644 index f7c315af91..0000000000 --- a/src/southbridge/nvidia/ck804/usb.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "chip.h" - -static void usb1_init(struct device *dev) -{ - struct southbridge_nvidia_ck804_config const *conf = dev->chip_info; - - if (!conf->usb1_hc_reset) - return; - - /* - * Somehow the warm reset does not really reset the USB - * controller. Later, during boot, when the Bus Master bit is - * set, the USB controller trashes the memory, causing weird - * misbehavior. Was detected on Sun Ultra40, where mptable - * was damaged. - */ - u32 bar0 = pci_read_config32(dev, 0x10); - u32 *regs = (u32 *) (bar0 & ~0xfff); - - /* OHCI USB HCCommandStatus Register, HostControllerReset bit */ - regs[2] |= 1; -} - -static struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb1_init, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver usb_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_USB, -}; diff --git a/src/southbridge/nvidia/ck804/usb2.c b/src/southbridge/nvidia/ck804/usb2.c deleted file mode 100644 index 47643aefbf..0000000000 --- a/src/southbridge/nvidia/ck804/usb2.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "chip.h" - -static void usb2_init(struct device *dev) -{ - u32 dword; - - dword = pci_read_config32(dev, 0xf8); - dword |= 40; - pci_write_config32(dev, 0xf8, dword); -} - -static struct device_operations usb2_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb2_init, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver usb2_driver __pci_driver = { - .ops = &usb2_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_USB2, -}; |