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authorMyles Watson <mylesgw@gmail.com>2009-11-06 17:02:51 +0000
committerMyles Watson <mylesgw@gmail.com>2009-11-06 17:02:51 +0000
commit1d6d45e3c98e16cbb86915483f771a7bf0e9a633 (patch)
tree38eca17371ca6c9e47b0b403d016eb163327b01b /src/southbridge
parent637309d65e6448d34cc92d44f92a93324c154e79 (diff)
downloadcoreboot-1d6d45e3c98e16cbb86915483f771a7bf0e9a633.tar.xz
Split the two usages of __ROMCC__:
__ROMCC__ now means "Don't use prototypes, since romcc doesn't support them." __PRE_RAM__ means "Use simpler versions of functions, and no device tree." There are probably some places where both are tested, but only one is needed. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/cs5530/cs5530.h2
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb.h2
-rw-r--r--src/southbridge/intel/i82801ca/i82801ca.h2
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.h2
-rw-r--r--src/southbridge/intel/i82801xx/i82801xx.h2
5 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/amd/cs5530/cs5530.h b/src/southbridge/amd/cs5530/cs5530.h
index 107b6f26e5..283b64de33 100644
--- a/src/southbridge/amd/cs5530/cs5530.h
+++ b/src/southbridge/amd/cs5530/cs5530.h
@@ -21,7 +21,7 @@
#ifndef SOUTHBRIDGE_AMD_CS5530_CS5530_H
#define SOUTHBRIDGE_AMD_CS5530_CS5530_H
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#include "chip.h"
void cs5530_enable(device_t dev);
#endif
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index 00c19e04e3..f105571380 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -21,7 +21,7 @@
#ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
#define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#include "chip.h"
void i82371eb_enable(device_t dev);
void i82371eb_hard_reset(void);
diff --git a/src/southbridge/intel/i82801ca/i82801ca.h b/src/southbridge/intel/i82801ca/i82801ca.h
index 59056f29df..a761056bff 100644
--- a/src/southbridge/intel/i82801ca/i82801ca.h
+++ b/src/southbridge/intel/i82801ca/i82801ca.h
@@ -1,7 +1,7 @@
#ifndef I82801CA_H
#define I82801CA_H
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801ca_enable(device_t dev);
#endif
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 9b54fc6008..5c29c9ea62 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -41,7 +41,7 @@
/* __ROMCC__ is set by auto.c to make sure
* none of the stage2 data structures are included.
*/
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801gx_enable(device_t dev);
#endif
diff --git a/src/southbridge/intel/i82801xx/i82801xx.h b/src/southbridge/intel/i82801xx/i82801xx.h
index 27ce21c207..d90cc32b37 100644
--- a/src/southbridge/intel/i82801xx/i82801xx.h
+++ b/src/southbridge/intel/i82801xx/i82801xx.h
@@ -21,7 +21,7 @@
#ifndef SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
#define SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801xx_enable(device_t dev);
#endif