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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-01-24 15:10:09 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-09-17 08:16:22 +0000
commit503f9fda30d44f75246fdabce4d5eb371da3c2d0 (patch)
treebdea83feae32c0d04225f289b097d53cc40ae662 /src/southbridge
parent8b8fbafb847c412d95089c639ffafd3317acc1d8 (diff)
downloadcoreboot-503f9fda30d44f75246fdabce4d5eb371da3c2d0.tar.xz
binaryPI: Move Hudson firmware higher in CBFS
Move it above 'AGESA' to increase the maximum continuous free space in CBFS from 5.3 MiB to 5.8 MiB. Also fixes build for cases where CBFS_SIZE < ROM_SIZE, thus allowing FMAP regions. NOTE: Due to off-by-one error in binaryPI, offset 0xFFFA0000 that amdfwtool advertises fails for xHCI firmware loading. Change-Id: Ic78520f4248f0943769e66a8825911c0ddcc368c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/pi/hudson/Makefile.inc5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index a7fcd9907c..cfe800d555 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -72,7 +72,11 @@ smm-y += smi_util.c
#
# EC ROM should be 64K aligned.
+ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1)
+else
+HUDSON_FWM_POSITION=0xfff20000
+endif
ifeq ($(CONFIG_HUDSON_PSP), y)
@@ -191,6 +195,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \
$(OPT_2SMUFIRMWARE2_FN_FILE) \
$(OPT_2SMUSCS_FILE) \
--flashsize $(CONFIG_ROM_SIZE) \
+ --location $(HUDSON_FWM_POSITION) \
--output $@
ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)