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authorAngel Pons <th3fanbus@gmail.com>2020-07-02 22:47:45 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-11 23:11:33 +0000
commit517bc99db1ece3f3904534e9f0d5d3b28eb4815b (patch)
treecc430efa309d99d9ae7fba64e52bd20403ef948a /src/southbridge
parenta0a94d8c647af574374b718542bb932a76431376 (diff)
downloadcoreboot-517bc99db1ece3f3904534e9f0d5d3b28eb4815b.tar.xz
sb/intel/i82801dx: Correct SMBUS_IO_BASE value
The current value of 0x1000 would overlap the first PCI bridge IO window. As we commonly reserve IO range 0x0 .. 0x1000 for LPC and integrated device use, change SMBUS_IO_BASE to 0x400. This is the prevalent value among Intel southbridges, too. Change-Id: I5c299f001f9012d6766b155a2f5def5cff6e88d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43023 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/i82801dx/i82801dx.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index d5f09aa61f..cf852740f9 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -94,7 +94,7 @@ void aseg_smm_lock(void);
#define RTC_FAILED (1 <<2)
-#define SMBUS_IO_BASE 0x1000
+#define SMBUS_IO_BASE 0x400
#define PM1_STS 0x00
#define WAK_STS (1 << 15)