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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-06-06 12:53:03 +0300
committerRonald G. Minnich <rminnich@gmail.com>2013-06-12 05:20:54 +0200
commit5272a5feb74075da2edf2056f3d737543d0890b1 (patch)
treef83c5f059d34a00c47e6896477db96a332c47c48 /src/southbridge
parent1b7fd08ca174e3a3d69feeb7c4105f93c5d4687a (diff)
downloadcoreboot-5272a5feb74075da2edf2056f3d737543d0890b1.tar.xz
usbdebug: Drop printk within console_init()
In case with EARLY_CONSOLE, this printk is called before any other console is configured to transmit data. This outputs garbage on CONSOLE_SERIAL as baudrate is not yet programmed. For case without EARLY_CONSOLE, the order in which different console drivers initialize is obscure. Might sometimes work properly. Change-Id: I3792161e0a6dc17e17262048cc9136044dd69dc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3384 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/bd82x6x/usb_debug.c1
-rw-r--r--src/southbridge/intel/i82801gx/usb_debug.c1
-rw-r--r--src/southbridge/intel/lynxpoint/usb_debug.c1
-rw-r--r--src/southbridge/intel/sch/usb_debug.c1
4 files changed, 0 insertions, 4 deletions
diff --git a/src/southbridge/intel/bd82x6x/usb_debug.c b/src/southbridge/intel/bd82x6x/usb_debug.c
index e075a76195..38f144b02a 100644
--- a/src/southbridge/intel/bd82x6x/usb_debug.c
+++ b/src/southbridge/intel/bd82x6x/usb_debug.c
@@ -38,7 +38,6 @@ void enable_usbdebug(unsigned int port)
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Force ownership of the Debug Port to the EHCI controller. */
- printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
dbgctl |= (1 << 30);
write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
diff --git a/src/southbridge/intel/i82801gx/usb_debug.c b/src/southbridge/intel/i82801gx/usb_debug.c
index f447f7bb84..bdea889854 100644
--- a/src/southbridge/intel/i82801gx/usb_debug.c
+++ b/src/southbridge/intel/i82801gx/usb_debug.c
@@ -45,7 +45,6 @@ void enable_usbdebug(unsigned int port)
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Force ownership of the Debug Port to the EHCI controller. */
- printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
dbgctl |= (1 << 30);
write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
diff --git a/src/southbridge/intel/lynxpoint/usb_debug.c b/src/southbridge/intel/lynxpoint/usb_debug.c
index d8da7b5484..022cde3736 100644
--- a/src/southbridge/intel/lynxpoint/usb_debug.c
+++ b/src/southbridge/intel/lynxpoint/usb_debug.c
@@ -42,7 +42,6 @@ void enable_usbdebug(unsigned int port)
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Force ownership of the Debug Port to the EHCI controller. */
- printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
dbgctl |= (1 << 30);
write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
diff --git a/src/southbridge/intel/sch/usb_debug.c b/src/southbridge/intel/sch/usb_debug.c
index 4189716c08..fb436b5af7 100644
--- a/src/southbridge/intel/sch/usb_debug.c
+++ b/src/southbridge/intel/sch/usb_debug.c
@@ -41,7 +41,6 @@ void enable_usbdebug(unsigned int port)
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Force ownership of the Debug Port to the EHCI controller. */
- printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
dbgctl |= (1 << 30);
write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);