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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-12-29 10:28:08 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-12-30 21:35:54 +0000 |
| commit | 581383aaedd254cc6024eef3b3ef976222370583 (patch) | |
| tree | 1663d4417c59984fe2c3bd4b847e3dfdf4c0c243 /src/southbridge | |
| parent | 3521e260e3477b3c49835eb2330671e0bc7abe65 (diff) | |
| download | coreboot-581383aaedd254cc6024eef3b3ef976222370583.tar.xz | |
soc/intel: Fix ugly preprocessor macro
Macro hides that dev_find_slot() takes two arguments.
Change-Id: I639af31b9d4a2d702dfd2baebddbb8352e8bf9b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/acpi.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/soc.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index efe5412c9f..fbdc6e320b 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -34,7 +34,7 @@ typedef struct southbridge_intel_fsp_rangeley_config config_t; void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - struct device *lpcdev = dev_find_slot(SOC_LPC_DEVFN); + struct device *lpcdev = dev_find_slot(0, SOC_LPC_DEVFN); u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; config_t *config = lpcdev->chip_info; diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index ffadee4bf2..02e410d8e7 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -92,7 +92,7 @@ void rangeley_sb_early_initialization(void); /* PCI Configuration Space (D31:F0): LPC */ #define SOC_LPC_DEV PCI_DEV(0, 0x1f, 0) -#define SOC_LPC_DEVFN 0, PCI_DEVFN(0x1f,0) +#define SOC_LPC_DEVFN PCI_DEVFN(0x1f, 0) /* Southbridge IO BARs */ |