summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
authorYinghai Lu <yinghai.lu@amd.com>2006-12-20 20:15:33 +0000
committerYinghai Lu <yinghailu@gmail.com>2006-12-20 20:15:33 +0000
commit6c3874e8f880d6d9e4f3012d38ddd1f34ff2ec18 (patch)
tree539aa9949d9f2c6543d007e2b6fad2db9038ae8c /src/southbridge
parentc2c86465849189b267de215bad3d9109f5740e15 (diff)
downloadcoreboot-6c3874e8f880d6d9e4f3012d38ddd1f34ff2ec18.tar.xz
ck804 pref mem 4G above support
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Acked-by: Yinghai Lu <yinghai.lu@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/nvidia/ck804/ck804_pci.c25
1 files changed, 24 insertions, 1 deletions
diff --git a/src/southbridge/nvidia/ck804/ck804_pci.c b/src/southbridge/nvidia/ck804/ck804_pci.c
index 34e2e9c970..b2477c1de6 100644
--- a/src/southbridge/nvidia/ck804/ck804_pci.c
+++ b/src/southbridge/nvidia/ck804/ck804_pci.c
@@ -14,6 +14,10 @@ static void pci_init(struct device *dev)
{
uint32_t dword;
+#if CONFIG_PCI_64BIT_PREF_MEM == 1
+ device_t pci_domain_dev;
+ struct resource *mem1, *mem2;
+#endif
/* System error enable */
dword = pci_read_config32(dev, 0x04);
@@ -34,8 +38,27 @@ static void pci_init(struct device *dev)
pci_write_config32(dev, 0x4c, dword);
#endif
+#if CONFIG_PCI_64BIT_PREF_MEM == 1
+ pci_domain_dev = dev->bus->dev;
+ while(pci_domain_dev) {
+ if(pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) break;
+ pci_domain_dev = pci_domain_dev->bus->dev;
+ }
+
+ if(!pci_domain_dev) return; // impossiable
+ mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit
+ mem2 = find_resource(pci_domain_dev, 2); // mem
+ if(mem1->base > mem2->base) {
+ dword = mem2->base & (0xffff0000UL);
+ printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base);
+ } else {
+ dword = mem1->base & (0xffff0000UL);
+ printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", mem1->base);
+ }
+#else
dword = dev_root.resource[1].base & (0xffff0000UL);
- printk_debug("dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base);
+ printk_debug("dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base);
+#endif
printk_debug("[0x50] <-- 0x%08x\n", dword);
pci_write_config32(dev, 0x50, dword); //TOM