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authorJason Schildt <jschildt@gmail.com>2005-08-09 21:53:07 +0000
committerJason Schildt <jschildt@gmail.com>2005-08-09 21:53:07 +0000
commit6e44b422b3b26a4ce5b98fca12d0f3ef7d7af110 (patch)
tree4f94702f435949875bed8f725928cb571b7f40c8 /src/southbridge
parentdc2454eb944c2ea9201bd650d7bc9942d4653a6c (diff)
downloadcoreboot-6e44b422b3b26a4ce5b98fca12d0f3ef7d7af110.tar.xz
- Merge from linuxbios-lnxi (Linux Networx repository) up to public tree.
- Special version for HDAMA rev G with 33Mhz test and reboot out. - Support for CPU rev E, dual core, memory hoisting, - corrected an SST flashing problem. Kernel bug work around (NUMA) - added a Kernel bug work around for assigning CPU's to memory. r2@gog: svnadmin | 2005-08-03 08:47:54 -0600 Create local LNXI branch r1110@gog: jschildt | 2005-08-09 10:35:51 -0600 - Merge from Tom Zimmerman's additions to the hdama code for dual core and 33Mhz fix. r1111@gog: jschildt | 2005-08-09 11:07:11 -0600 Stable Release tag for HDAMA-1.1.8.10 and HDAMA-1.1.8.10LANL r1112@gog: jschildt | 2005-08-09 15:09:32 -0600 - temporarily removing hdama tag to update to public repository. Will reset tag after update. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/amd8111/Config.lb9
-rw-r--r--src/southbridge/amd/amd8111/amd8111_acpi.c5
-rw-r--r--src/southbridge/amd/amd8111/amd8111_lpc.c12
-rw-r--r--src/southbridge/amd/amd8111/amd8111_pci.c1
-rw-r--r--src/southbridge/amd/amd8111/amd8111_usb.c2
5 files changed, 13 insertions, 16 deletions
diff --git a/src/southbridge/amd/amd8111/Config.lb b/src/southbridge/amd/amd8111/Config.lb
index 9b53c26da4..a69229260b 100644
--- a/src/southbridge/amd/amd8111/Config.lb
+++ b/src/southbridge/amd/amd8111/Config.lb
@@ -1,12 +1,11 @@
config chip.h
driver amd8111.o
-#driver amd8111_usb.o
+driver amd8111_usb.o
driver amd8111_lpc.o
driver amd8111_ide.o
driver amd8111_acpi.o
-#driver amd8111_usb2.o
-#driver amd8111_ac97.o
-#driver amd8111_nic.o
+driver amd8111_usb2.o
+driver amd8111_ac97.o
+driver amd8111_nic.o
driver amd8111_pci.o
driver amd8111_smbus.o
-object amd8111_reset.o
diff --git a/src/southbridge/amd/amd8111/amd8111_acpi.c b/src/southbridge/amd/amd8111/amd8111_acpi.c
index 46a8e69510..209036adab 100644
--- a/src/southbridge/amd/amd8111/amd8111_acpi.c
+++ b/src/southbridge/amd/amd8111/amd8111_acpi.c
@@ -97,6 +97,7 @@ static void acpi_init(struct device *dev)
#endif
+ /* power after power fail */
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
@@ -106,7 +107,7 @@ static void acpi_init(struct device *dev)
}
pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
printk_info("set power %s after power fail\n", on?"on":"off");
-
+
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
@@ -177,7 +178,7 @@ static struct device_operations acpi_ops = {
.enable_resources = acpi_enable_resources,
.init = acpi_init,
.scan_bus = scan_static_bus,
-// .enable = amd8111_enable,
+ .enable = amd8111_enable,
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
};
diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c
index 65c1ccb013..49246d93d4 100644
--- a/src/southbridge/amd/amd8111/amd8111_lpc.c
+++ b/src/southbridge/amd/amd8111/amd8111_lpc.c
@@ -84,7 +84,7 @@ static void setup_ioapic(void)
return;
}
printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
- a->reg, a->value_low, a->value_high);
+ a->reg, a->value_low, a->value_high);
}
}
@@ -113,13 +113,9 @@ static void lpc_init(struct device *dev)
byte = pci_read_config8(dev, 0x46);
pci_write_config8(dev, 0x46, byte | (1<<0));
- /* power after power fail */
+ /* Enable 5Mib Rom window */
byte = pci_read_config8(dev, 0x43);
- if (pwr_on) {
- byte &= ~(1<<6);
- } else {
- byte |= (1<<6);
- }
+ byte |= 0xC0;
pci_write_config8(dev, 0x43, byte);
/* Enable Port 92 fast reset */
@@ -179,7 +175,7 @@ static void amd8111_lpc_enable_resources(device_t dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x70,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
diff --git a/src/southbridge/amd/amd8111/amd8111_pci.c b/src/southbridge/amd/amd8111/amd8111_pci.c
index 9fe1f98d32..b9a9b3578d 100644
--- a/src/southbridge/amd/amd8111/amd8111_pci.c
+++ b/src/southbridge/amd/amd8111/amd8111_pci.c
@@ -55,6 +55,7 @@ static struct device_operations pci_ops = {
.enable_resources = pci_bus_enable_resources,
.init = pci_init,
.scan_bus = pci_scan_bridge,
+ /* PCI Subordinate bus reset is not implemented */
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/amd/amd8111/amd8111_usb.c b/src/southbridge/amd/amd8111/amd8111_usb.c
index 5a01a97c58..ed9f133af2 100644
--- a/src/southbridge/amd/amd8111/amd8111_usb.c
+++ b/src/southbridge/amd/amd8111/amd8111_usb.c
@@ -26,7 +26,7 @@ static struct device_operations usb_ops = {
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = scan_static_bus,
-// .enable = amd8111_enable,
+ .enable = amd8111_enable,
.ops_pci = &lops_pci,
};