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| author | Li Cheng Sooi <li.cheng.sooi@intel.com> | 2017-02-24 02:52:13 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-03-09 16:41:18 +0100 |
| commit | 75d8d8da47a3cc759d7395f5b0ef91ba13a59e51 (patch) | |
| tree | 573ef1a93871c9122f806039df97a2b91318fa76 /src/southbridge | |
| parent | 6a740539d1005eb14d21da40d7d14ff7250da508 (diff) | |
| download | coreboot-75d8d8da47a3cc759d7395f5b0ef91ba13a59e51.tar.xz | |
soc/intel/skylake: Add GPIO macros for IOxAPIC and SCI
Add two GPIO macros:
1. PAD_CFG_GPI_APIC_EDGE allows a pin to be route to the
APIC with input assuming the events are edge triggered.
2. PAD_CFG_GPI_ACPI_SCI_LEVEL to route the general purpose
input to SCI assuming the events are level triggered.
Change-Id: I944a9abac66b7780b2336148ae8c7fa3a8410f3f
Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com>
Reviewed-on: https://review.coreboot.org/18533
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions