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authorAlexander Couzens <lynxis@fe80.eu>2015-04-16 02:00:21 +0200
committerPeter Stuge <peter@stuge.se>2015-09-02 21:11:10 +0000
commit7bf47eecd60415c5151cd9906947b5ef375f29de (patch)
treed7711e476db4648cedd90cc5b1559273fd947e0b /src/southbridge
parentef549a04c50aaef425b6f21324aa275d2e1318f4 (diff)
downloadcoreboot-7bf47eecd60415c5151cd9906947b5ef375f29de.tar.xz
southbridge/bd82x6x: use new ssdt sata port generator
Drop old incomplete, broken and hardcoded sata.asl properties. The new sata acpi generator only needs a proper defined device. Change-Id: I2be76097ebd27f2529e3fbbecefd314a0eea3cb0 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/9709 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/bd82x6x/Kconfig1
-rw-r--r--src/southbridge/intel/bd82x6x/acpi/sata.asl52
-rw-r--r--src/southbridge/intel/bd82x6x/sata.c9
3 files changed, 10 insertions, 52 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 6190879d76..3a68fec841 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -37,6 +37,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
select COMMON_FADT
+ select ACPI_SATA_GENERATOR
config EHCI_BAR
hex
diff --git a/src/southbridge/intel/bd82x6x/acpi/sata.asl b/src/southbridge/intel/bd82x6x/acpi/sata.asl
index fb685a38fb..00d30109cd 100644
--- a/src/southbridge/intel/bd82x6x/acpi/sata.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/sata.asl
@@ -26,56 +26,4 @@
Device (SATA)
{
Name (_ADR, 0x001f0002)
-
- Device (PRID)
- {
- Name (_ADR, 0)
-
- // Get Timing Mode
- Method (_GTM)
- {
- Name(PBUF, Buffer(20) {
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00 })
-
- CreateDwordField (PBUF, 0, PIO0)
- CreateDwordField (PBUF, 4, DMA0)
- CreateDwordField (PBUF, 8, PIO1)
- CreateDwordField (PBUF, 12, DMA1)
- CreateDwordField (PBUF, 16, FLAG)
-
- // TODO fill return structure
-
- Return (PBUF)
- }
-
- // Set Timing Mode
- Method (_STM, 3)
- {
- CreateDwordField (Arg0, 0, PIO0)
- CreateDwordField (Arg0, 4, DMA0)
- CreateDwordField (Arg0, 8, PIO1)
- CreateDwordField (Arg0, 12, DMA1)
- CreateDwordField (Arg0, 16, FLAG)
-
- // TODO: Do the deed
- }
-
- Device (DSK0)
- {
- Name (_ADR, 0)
- // TODO: _RMV ?
- // TODO: _GTF ?
- }
-
- Device (DSK1)
- {
- Name (_ADR, 1)
-
- // TODO: _RMV ?
- // TODO: _GTF ?
- }
-
- }
}
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 1cdc5e2b8b..66a4c561ae 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -25,6 +25,7 @@
#include <device/pci_ids.h>
#include "pch.h"
#include <pc80/mc146818rtc.h>
+#include <acpi/sata.h>
typedef struct southbridge_intel_bd82x6x_config config_t;
@@ -247,6 +248,12 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
+static void sata_fill_ssdt(device_t dev)
+{
+ config_t *config = dev->chip_info;
+ generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map);
+}
+
static struct pci_operations sata_pci_ops = {
.set_subsystem = sata_set_subsystem,
};
@@ -255,6 +262,8 @@ static struct device_operations sata_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
+ .acpi_fill_ssdt_generator
+ = sata_fill_ssdt,
.init = sata_init,
.enable = sata_enable,
.scan_bus = 0,