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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-11-20 08:24:12 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-01 05:48:11 +0100
commit7d09cfcf749c1c0fd1c3791585065b39ec1a3433 (patch)
tree9a031577ff4133bed52299b5e6574274a168ae4c /src/southbridge
parentde43dd631402e326bbfb3fa6fa3bd92cb497871c (diff)
downloadcoreboot-7d09cfcf749c1c0fd1c3791585065b39ec1a3433.tar.xz
AGESA: Use explicit PCI IO config access in bootblock
This allows us to set MMCONF_SUPPORT_DEFAULT since we enable MMCONF early in romstage. Change-Id: I994bb257db96300c2eb8872be6fae2a92bbabab4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17531 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/agesa/hudson/bootblock.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c
index ff5219920d..32b129862d 100644
--- a/src/southbridge/amd/agesa/hudson/bootblock.c
+++ b/src/southbridge/amd/agesa/hudson/bootblock.c
@@ -34,15 +34,15 @@ static void hudson_enable_rom(void)
dev = PCI_DEV(0, 0x14, 3);
/* Decode variable LPC ROM address ranges 1 and 2. */
- reg8 = pci_read_config8(dev, 0x48);
+ reg8 = pci_io_read_config8(dev, 0x48);
reg8 |= (1 << 3) | (1 << 4);
- pci_write_config8(dev, 0x48, reg8);
+ pci_io_write_config8(dev, 0x48, reg8);
/* LPC ROM address range 1: */
/* Enable LPC ROM range mirroring start at 0x000e(0000). */
- pci_write_config16(dev, 0x68, 0x000e);
+ pci_io_write_config16(dev, 0x68, 0x000e);
/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
- pci_write_config16(dev, 0x6a, 0x000f);
+ pci_io_write_config16(dev, 0x6a, 0x000f);
/* LPC ROM address range 2: */
/*
@@ -52,9 +52,9 @@ static void hudson_enable_rom(void)
* 0xffe0(0000): 2MB
* 0xffc0(0000): 4MB
*/
- pci_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
+ pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
/* Enable LPC ROM range end at 0xffff(ffff). */
- pci_write_config16(dev, 0x6e, 0xffff);
+ pci_io_write_config16(dev, 0x6e, 0xffff);
}
static void bootblock_southbridge_init(void)