Improve support for the Intel 82371FB/SB/AB/EB/MB southbridge(s):

 - Implement ISA related support:
   - Initialize the RTC
   - Enable access to all BIOS regions (but _not_ write access to ROM)
   - Enable ISA (not EIO) support
   - Without the *_isa.c file, the Super I/O init is never performed
 - Improve IDE support:
   - Add config option to enable Ultra DMA/33 for each disk
   - Add config option to enable legacy IDE port access
 - Implement hard reset support
 - Implement USB controller support
 - Various code cleanups and improvements

The code partially supports southbridges other than the 82371EB (but
which are very similar), more complete support will follow.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

10 files changed, 415 insertions, 77 deletions

diff --git a/src/southbridge/intel/i82371eb/Config.lb b/src/southbridge/intel/i82371eb/Config.lb
index 4958449902..3517114986 100644
--- a/src/southbridge/intel/i82371eb/Config.lb
+++ b/src/southbridge/intel/i82371eb/Config.lb
@@ -19,8 +19,9 @@
 ##
 
 config chip.h
-
 driver i82371eb.o
-driver i82371eb_smbus.o
+driver i82371eb_isa.o
 driver i82371eb_ide.o
-
+driver i82371eb_usb.o
+driver i82371eb_smbus.o
+driver i82371eb_reset.o
diff --git a/src/southbridge/intel/i82371eb/chip.h b/src/southbridge/intel/i82371eb/chip.h
index 2dac6d14ec..7f6cbaa6fb 100644
--- a/src/southbridge/intel/i82371eb/chip.h
+++ b/src/southbridge/intel/i82371eb/chip.h
@@ -23,12 +23,17 @@
 
 #include <device/device.h>
 
-extern struct chip_operations southbridge_intel_i82371eb_ops;
+extern const struct chip_operations southbridge_intel_i82371eb_ops;
 
 struct southbridge_intel_i82371eb_config {
 	int ide0_enable:1;
+	int ide0_drive0_udma33_enable:1;
+	int ide0_drive1_udma33_enable:1;
 	int ide1_enable:1;
+	int ide1_drive0_udma33_enable:1;
+	int ide1_drive1_udma33_enable:1;
+	int ide_legacy_enable:1;
 	int usb_enable:1;
 };
 
-#endif				/* SOUTHBRIDGE_INTEL_I82371EB_CHIP_H */
+#endif /* SOUTHBRIDGE_INTEL_I82371EB_CHIP_H */
diff --git a/src/southbridge/intel/i82371eb/i82371eb.c b/src/southbridge/intel/i82371eb/i82371eb.c
index ab982cf65a..3a7b8d201b 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.c
+++ b/src/southbridge/intel/i82371eb/i82371eb.c
@@ -18,46 +18,47 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* Datasheet:
+/* Note: This code supports the 82371FB/SB/MX/AB/EB/MB and 82437MX. */
+
+/* Datasheets:
+ *   - Name: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
+ *   - URL: http://www.intel.com/design/intarch/datashts/290550.htm
+ *   - PDF: http://download.intel.com/design/intarch/datashts/29055002.pdf
+ *   - Date: April 1997
+ *   - Order Number: 290550-002
+ *
+ *   - Name: 82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE Xcelerator
+ *           Specification Update
+ *   - URL: http://www.intel.com/design/chipsets/specupdt/297658.htm
+ *   - PDF: http://download.intel.com/design/chipsets/specupdt/29765801.pdf
+ *   - Date: March 1998
+ *   - Order Number: 297658-004
+ *
  *   - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
+ *           (applies to 82371AB/EB/MB, a.k.a. PIIX4/PIIX4E/PIIX4M)
  *   - URL: http://www.intel.com/design/intarch/datashts/290562.htm
  *   - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
+ *   - Date: April 1997
  *   - Order Number: 290562-001
+ *
+ *   - Name: 82371AB/EB/MB (PIIX4/PIIX4E/PIIX4M) Specification Update
+ *   - URL: http://www.intel.com/design/chipsets/specupdt/297738.htm
+ *   - PDF: http://www.intel.com/design/chipsets/specupdt/29773817.pdf
+ *   - Date: January 2002
+ *   - Order Number: 297738-017
  */
 
-#include <console/console.h>
+/* TODO: List the other datasheets. */
+
 #include <device/device.h>
-#include <device/pci.h>
 #include "i82371eb.h"
 
-/**
- * Enable access to all BIOS regions. Do not enable write access to the ROM.
- *
- * XBCS register bits:
- * - Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
- *              FFF00000-FFF7FFFF are forwarded to ISA).
- * - Set bit 7: Extended BIOS Enable (PCI master accesses to
- *              FFF80000-FFFDFFFF are forwarded to ISA).
- * - Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
- *              the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
- *              of 1 Mbyte, or the aliases at the top of 4 Gbyte
- *              (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
- * - Bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
- *
- * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
- *
- * @param dev The device to use.
- */
-void i82371eb_enable(device_t dev)
+void i82371eb_enable(struct device *dev)
 {
-	uint16_t reg;
-
-	reg = pci_read_config16(dev, XBCS);
-	reg |= 0x2c0;
-	pci_write_config16(dev, XBCS, reg);
+	/* TODO: Nothing to do? */
 }
 
-struct chip_operations southbridge_intel_i82371eb_ops = {
-	CHIP_NAME("Intel 82371EB Southbridge")
+const struct chip_operations southbridge_intel_i82371eb_ops = {
+	CHIP_NAME("Intel 82371FB/SB/MX/AB/EB/MB Southbridge")
 	.enable_dev = i82371eb_enable,
 };
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index 0693d4d564..7b8cce0e38 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -18,27 +18,58 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#ifndef SOUTHBRIDGE_INTEL_I82371EB_H
-#define SOUTHBRIDGE_INTEL_I82371EB_H
+#ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
+#define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
 
 #ifndef __ROMCC__
 #include "chip.h"
 void i82371eb_enable(device_t dev);
 #endif
 
-#define XBCS		0x4e	/* X-Bus Chip Select register */
+/* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the
+ * 'reg' variable, otherwise it clears those bits.
+ *
+ * Examples:
+ * reg16 = ONOFF(conf->ide0_enable, reg16, (1 << 5));
+ * reg16 = ONOFF(conf->ide0_enable, reg16, (FOO | BAR));
+ */
+/* TODO: Move into some global header file? */
+#define ONOFF(cond,reg,bits) ((cond) ? ((reg) | (bits)) : ((reg) & ~(bits)))
 
-/* SMBus */
-#define SMBBA		0x90	/* SMBus Base Address */
-#define SMBHSTCFG	0xd2	/* SMBus Host Configuration */
+#define XBCS		0x4e	/* X-Bus chip select register */
+#define GENCFG		0xb0	/* General configuration register */
+#define RC		0xcf9	/* Reset control register */
 
 /* IDE */
 #define IDETIM_PRI	0x40	/* IDE timing register, primary channel */
 #define IDETIM_SEC	0x42	/* IDE timing register, secondary channel */
+#define UDMACTL		0x48	/* Ultra DMA/33 control register */
+#define UDMATIM		0x4a	/* Ultra DMA/33 timing register */
+
+/* SMBus */
+#define SMBBA		0x90	/* SMBus base address */
+#define SMBHSTCFG	0xd2	/* SMBus host configuration */
+
+/* Power management (ACPI) */
+#define PMBA		0x40	/* Power management base address */
+#define PMREGMISC	0x80	/* Miscellaneous power management */
 
 /* Bit definitions */
-#define	IOSE			(1 << 0)	/* I/O Space Enable */
-#define SMB_HST_EN		(1 << 0)	/* Host Interface Enable */
-#define IDE_DECODE_ENABLE	(1 << 15)	/* IDE Decode Enable */
+#define EXT_BIOS_ENABLE_1MB	(1 << 9)  /* 1-Meg Extended BIOS Enable */
+#define EXT_BIOS_ENABLE		(1 << 7)  /* Extended BIOS Enable */
+#define LOWER_BIOS_ENABLE	(1 << 6)  /* Lower BIOS Enable */
+#define WRITE_PROTECT_ENABLE	(1 << 2)  /* Write Protect Enable */
+#define SRST			(1 << 1)  /* System Reset */
+#define RCPU			(1 << 2)  /* Reset CPU */
+#define SMB_HST_EN		(1 << 0)  /* Host Interface Enable */
+#define IDE_DECODE_ENABLE	(1 << 15) /* IDE Decode Enable */
+#define DTE0			(1 << 3)  /* DMA Timing Enable Only, drive 0 */
+#define DTE1			(1 << 7)  /* DMA Timing Enable Only, drive 1 */
+#define PSDE0			(1 << 0)  /* Primary Drive 0 UDMA/33 */
+#define PSDE1			(1 << 1)  /* Primary Drive 1 UDMA/33 */
+#define SSDE0			(1 << 2)  /* Secondary Drive 0 UDMA/33 */
+#define SSDE1			(1 << 3)  /* Secondary Drive 1 UDMA/33 */
+#define ISA			(1 << 0)  /* Select ISA */
+#define EIO			(0 << 0)  /* Select EIO */
 
-#endif				/* SOUTHBRIDGE_INTEL_I82371EB_H */
+#endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */
diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
index 30b6e6a320..fc6e199ea6 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
@@ -20,6 +20,7 @@
 
 /* TODO: Implement smbus_write_byte(), smbus_recv_byte(), smbus_send_byte(). */
 
+#include <stdint.h>
 #include <device/pci_ids.h>
 #include "i82371eb.h"
 #include "i82371eb_smbus.h"
@@ -29,35 +30,36 @@
 static void enable_smbus(void)
 {
 	device_t dev;
-	uint8_t reg8;
-	uint16_t reg16;
+	u8 reg8;
+	u16 reg16;
 
+	/* Check for SMBus device PCI ID on the 82371AB/EB/MB. */
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
 				PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
 
-	if (dev == PCI_DEV_INVALID) {
+	if (dev == PCI_DEV_INVALID)
 		die("SMBus controller not found\r\n");
-	}
+
 	print_spew("SMBus controller enabled\r\n");
 
 	/* Set the SMBus I/O base. */
 	pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1);
 
-	/* Enable the SMBus Controller Host Interface. */
+	/* Enable the SMBus controller host interface. */
 	reg8 = pci_read_config8(dev, SMBHSTCFG);
 	reg8 |= SMB_HST_EN;
 	pci_write_config8(dev, SMBHSTCFG, reg8);
 
 	/* Enable access to the SMBus I/O space. */
 	reg16 = pci_read_config16(dev, PCI_COMMAND);
-	reg16 |= IOSE;
+	reg16 |= PCI_COMMAND_IO;
 	pci_write_config16(dev, PCI_COMMAND, reg16);
 
 	/* Clear any lingering errors, so the transaction will run. */
 	outb(inb(SMBUS_IO_BASE + SMBHST_STATUS), SMBUS_IO_BASE + SMBHST_STATUS);
 }
 
-static int smbus_read_byte(unsigned int device, unsigned int address)
+static int smbus_read_byte(u8 device, u8 address)
 {
 	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
diff --git a/src/southbridge/intel/i82371eb/i82371eb_ide.c b/src/southbridge/intel/i82371eb/i82371eb_ide.c
index 9e35927260..c255a237e2 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_ide.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_ide.c
@@ -18,6 +18,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+/* TODO: Check if this really works for all of the southbridges. */
+
+#include <stdint.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -28,49 +31,171 @@
  * Initialize the IDE controller.
  *
  * Depending on the configuration variables 'ide0_enable' and 'ide1_enable'
- * we enable or disable the primary and secondary IDE interface, respectively.
+ * enable or disable the primary and secondary IDE interface, respectively.
+ *
+ * Depending on the configuration variable 'ide_legacy_enable' enable or
+ * disable access to the legacy IDE ports and the PCI Bus Master IDE I/O
+ * registers (this is required for e.g. FILO).
  *
  * @param dev The device to use.
  */
-static void ide_init(struct device *dev)
+static void ide_init_enable(struct device *dev)
 {
-	uint16_t reg;
+	u16 reg16;
 	struct southbridge_intel_i82371eb_config *conf = dev->chip_info;
 
 	/* Enable/disable the primary IDE interface. */
-	reg = pci_read_config16(dev, IDETIM_PRI);
+	reg16 = pci_read_config16(dev, IDETIM_PRI);
+	reg16 = ONOFF(conf->ide0_enable, reg16, IDE_DECODE_ENABLE);
+	pci_write_config16(dev, IDETIM_PRI, reg16);
+	printk_debug("IDE: %s: %s\n", "Primary IDE interface",
+		     conf->ide0_enable ? "on" : "off");
+
+	/* Enable/disable the secondary IDE interface. */
+	reg16 = pci_read_config16(dev, IDETIM_SEC);
+	reg16 = ONOFF(conf->ide1_enable, reg16, IDE_DECODE_ENABLE);
+	pci_write_config16(dev, IDETIM_SEC, reg16);
+	printk_debug("IDE: %s: %s\n", "Secondary IDE interface",
+		     conf->ide1_enable ? "on" : "off");
+
+	/* Enable access to the legacy IDE ports (both primary and secondary),
+	 * and the PCI Bus Master IDE I/O registers.
+	 * Only do this if at least one IDE interface is enabled.
+	 */
+	if (conf->ide0_enable || conf->ide1_enable) {
+		reg16 = pci_read_config16(dev, PCI_COMMAND);
+		reg16 = ONOFF(conf->ide_legacy_enable, reg16,
+			      (PCI_COMMAND_IO | PCI_COMMAND_MASTER));
+		pci_write_config16(dev, PCI_COMMAND, reg16);
+		printk_debug("IDE: Access to legacy IDE ports: %s\n",
+			     conf->ide_legacy_enable ? "on" : "off");
+	}
+}
+
+/**
+ * Initialize the Ultra DMA/33 support of the IDE controller.
+ *
+ * Depending on the configuration variables 'ide0_drive0_udma33_enable',
+ * 'ide0_drive1_udma33_enable', 'ide1_drive0_udma33_enable', and
+ * 'ide1_drive1_udma33_enable' enable or disable Ultra DMA/33 support for
+ * the respective IDE controller and drive.
+ *
+ * Only do that if the respective controller is actually enabled, of course.
+ *
+ * @param dev The device to use.
+ */
+static void ide_init_udma33(struct device *dev)
+{
+	u8 reg8;
+	struct southbridge_intel_i82371eb_config *conf = dev->chip_info;
+
+	/* Enable/disable UDMA/33 operation (primary IDE interface). */
 	if (conf->ide0_enable) {
-		reg |= IDE_DECODE_ENABLE;
-		print_info("Primary IDE interface enabled\n");
-	} else {
-		reg &= ~(IDE_DECODE_ENABLE);
-		print_info("Primary IDE interface disabled\n");
+		reg8 = pci_read_config8(dev, UDMACTL);
+		reg8 = ONOFF(conf->ide0_drive0_udma33_enable, reg8, PSDE0);
+		reg8 = ONOFF(conf->ide0_drive1_udma33_enable, reg8, PSDE1);
+		pci_write_config8(dev, UDMACTL, reg8);
+
+		printk_debug("IDE: %s, drive %d: UDMA/33: %s\n",
+			     "Primary IDE interface", 0,
+			     conf->ide0_drive0_udma33_enable ? "on" : "off");
+		printk_debug("IDE: %s, drive %d: UDMA/33: %s\n",
+			     "Primary IDE interface", 1,
+			     conf->ide0_drive1_udma33_enable ? "on" : "off");
 	}
-	pci_write_config16(dev, IDETIM_PRI, reg);
 
-	/* Enable/disable the secondary IDE interface. */
-	reg = pci_read_config16(dev, IDETIM_SEC);
+	/* Enable/disable Ultra DMA/33 operation (secondary IDE interface). */
 	if (conf->ide1_enable) {
-		reg |= IDE_DECODE_ENABLE;
-		print_info("Secondary IDE interface enabled\n");
-	} else {
-		reg &= ~(IDE_DECODE_ENABLE);
-		print_info("Secondary IDE interface disabled\n");
+		reg8 = pci_read_config8(dev, UDMACTL);
+		reg8 = ONOFF(conf->ide1_drive0_udma33_enable, reg8, SSDE0);
+		reg8 = ONOFF(conf->ide1_drive1_udma33_enable, reg8, SSDE1);
+		pci_write_config8(dev, UDMACTL, reg8);
+
+		printk_debug("IDE: %s, drive %d: UDMA/33: %s\n",
+			     "Secondary IDE interface", 0,
+			     conf->ide1_drive0_udma33_enable ? "on" : "off");
+		printk_debug("IDE: %s, drive %d: UDMA/33: %s\n",
+			     "Secondary IDE interface", 1,
+			     conf->ide1_drive1_udma33_enable ? "on" : "off");
 	}
-	pci_write_config16(dev, IDETIM_SEC, reg);
 }
 
-static struct device_operations ide_ops = {
+/**
+ * IDE init for the Intel 82371FB/SB IDE controller.
+ *
+ * These devices do not support UDMA/33, so don't attempt to enable it.
+ *
+ * @param dev The device to use.
+ */
+static void ide_init_i82371fb_sb(struct device *dev)
+{
+	ide_init_enable(dev);
+}
+
+/**
+ * IDE init for the Intel 82371AB/EB/MB IDE controller.
+ *
+ * @param dev The device to use.
+ */
+static void ide_init_i82371ab_eb_mb(struct device *dev)
+{
+	ide_init_enable(dev);
+	ide_init_udma33(dev);
+}
+
+/* Intel 82371FB/SB */
+static const struct device_operations ide_ops_fb_sb = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= ide_init_i82371fb_sb,
+	.scan_bus		= 0,
+	.enable			= 0,
+	.ops_pci		= 0, /* No subsystem IDs on 82371XX! */
+};
+
+/* Intel 82371AB/EB/MB */
+static const struct device_operations ide_ops_ab_eb_mb = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-	.init			= ide_init,
+	.init			= ide_init_i82371ab_eb_mb,
 	.scan_bus		= 0,
-	.ops_pci		= 0, /* No subsystem IDs on 82371EB! */
+	.enable			= 0,
+	.ops_pci		= 0, /* No subsystem IDs on 82371XX! */
+};
+
+/* Intel 82371FB (PIIX) */
+static const struct pci_driver ide_driver_fb __pci_driver = {
+	.ops	= &ide_ops_fb_sb,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371FB_IDE,
+};
+
+/* Intel 82371SB (PIIX3) */
+static const struct pci_driver ide_driver_sb __pci_driver = {
+	.ops	= &ide_ops_fb_sb,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371SB_IDE,
+};
+
+/* Intel 82371MX (MPIIX) */
+static const struct pci_driver ide_driver_mx __pci_driver = {
+	.ops	= &ide_ops_fb_sb,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371MX_ISA_IDE,
+};
+
+/* Intel 82437MX (part of the 430MX chipset) */
+static const struct pci_driver ide_driver_82437mx __pci_driver = {
+	.ops	= &ide_ops_fb_sb,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82437MX_ISA_IDE,
 };
 
-static const struct pci_driver ide_driver __pci_driver = {
-	.ops	= &ide_ops,
+/* Intel 82371AB/EB/MB */
+static const struct pci_driver ide_driver_ab_eb_mb __pci_driver = {
+	.ops	= &ide_ops_ab_eb_mb,
 	.vendor	= PCI_VENDOR_ID_INTEL,
 	.device	= PCI_DEVICE_ID_INTEL_82371AB_IDE,
 };
diff --git a/src/southbridge/intel/i82371eb/i82371eb_isa.c b/src/southbridge/intel/i82371eb/i82371eb_isa.c
new file mode 100644
index 0000000000..12a26db60d
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/i82371eb_isa.c
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/isa-dma.h>
+#include <pc80/mc146818rtc.h>
+#include "i82371eb.h"
+
+static void isa_init(struct device *dev)
+{
+	u16 reg16;
+	u32 reg32;
+
+	/* Initialize the real time clock (RTC). */
+	rtc_init(0);
+
+	/* Enable access to all BIOS regions. */
+	reg16 = pci_read_config16(dev, XBCS);
+	reg16 |= LOWER_BIOS_ENABLE;
+	reg16 |= EXT_BIOS_ENABLE;
+	reg16 |= EXT_BIOS_ENABLE_1MB;
+	reg16 &= ~(WRITE_PROTECT_ENABLE);	/* Disable ROM write access. */
+	pci_write_config16(dev, XBCS, reg16);
+
+	/*
+	 * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)
+	 * bus, which is a subset of ISA. We select the full ISA bus here.
+	 */
+	reg32 = pci_read_config32(dev, GENCFG);
+	reg32 |= ISA;	/* Select ISA, not EIO. */
+	pci_write_config16(dev, GENCFG, reg32);
+
+	/* Initialize ISA DMA. */
+	isa_dma_init();
+}
+
+static const struct device_operations isa_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= isa_init,
+	.scan_bus		= scan_static_bus,	/* TODO: Needed? */
+	.enable			= 0,
+	.ops_pci		= 0, /* No subsystem IDs on 82371EB! */
+};
+
+static const struct pci_driver isa_driver __pci_driver = {
+	.ops	= &isa_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371AB_ISA,
+};
diff --git a/src/southbridge/intel/i82371eb/i82371eb_reset.c b/src/southbridge/intel/i82371eb/i82371eb_reset.c
new file mode 100644
index 0000000000..5ed4697594
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/i82371eb_reset.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include "i82371eb.h"
+
+/**
+ * Initiate a hard reset.
+ */
+void i82371eb_hard_reset(void)
+{
+	outb(SRST | RCPU, RC);
+}
diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_smbus.c
index 838380d7bb..ae1b29335a 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_smbus.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_smbus.c
@@ -18,26 +18,31 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <stdint.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/smbus.h>
 #include "i82371eb.h"
 
-static struct smbus_bus_operations lops_smbus_bus = {
+/* TODO: Needed later? */
+static const struct smbus_bus_operations lops_smbus_bus = {
 };
 
-static struct device_operations smbus_ops = {
+static const struct device_operations smbus_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= 0,
 	.scan_bus		= scan_static_bus,
-	// .enable		= i82371eb_enable,	// TODO: Needed?
+	.enable			= 0,
 	.ops_pci		= 0, /* No subsystem IDs on 82371EB! */
 	.ops_smbus_bus		= &lops_smbus_bus,
 };
 
+/* Note: There's no SMBus on 82371FB/SB/MX and 82437MX. */
+
+/* Intel 82371AB/EB/MB */
 static const struct pci_driver smbus_driver __pci_driver = {
 	.ops	= &smbus_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
diff --git a/src/southbridge/intel/i82371eb/i82371eb_usb.c b/src/southbridge/intel/i82371eb/i82371eb_usb.c
new file mode 100644
index 0000000000..99c3a367da
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/i82371eb_usb.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82371eb.h"
+
+/**
+ * Initialize the USB (UHCI) controller.
+ *
+ * Depending on the configuration variable 'usb_enable', enable or
+ * disable the USB (UHCI) controller.
+ *
+ * @param dev The device to use.
+ */
+static void usb_init(struct device *dev)
+{
+	/* TODO: No special init needed? */
+}
+
+static const struct device_operations usb_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= usb_init,
+	.scan_bus		= 0,
+	.enable			= 0,
+	.ops_pci		= 0, /* No subsystem IDs on 82371EB! */
+};
+
+/* Note: No USB on 82371FB/MX (PIIX/MPIIX) and 82437MX. */
+
+/* Intel 82371SB (PIIX3) */
+static const struct pci_driver usb_driver_sb __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371SB_USB,
+};
+
+/* Intel 82371AB/EB/MB (PIIX4/PIIX4E/PIIX4M) */
+/* The 440MX (82443MX) consists of 82443BX + 82371EB (uses same PCI IDs). */
+static const struct pci_driver usb_driver_ab_eb_mb __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371AB_USB,
+};