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authorPatrick Georgi <patrick.georgi@coresystems.de>2010-09-08 10:58:02 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-09-08 10:58:02 +0000
commita4c0a1d6e6669736e101ada54b81d529f7c84cde (patch)
tree14fadad764d9d21dc9aa7b65ce270d8705e5121f /src/southbridge
parent24f83a76ae2608f7df0a11d80537fdc907f1e88c (diff)
downloadcoreboot-a4c0a1d6e6669736e101ada54b81d529f7c84cde.tar.xz
Make timer2 the default choice for TSC initialization.
For boards where timer2 is unusable, there's still the IO based initialization available using the Kconfig option TSC_CALIBRATE_WITH_IO Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Kevin O'Connor <kevin@koconnor.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/cs5536/Kconfig9
1 files changed, 1 insertions, 8 deletions
diff --git a/src/southbridge/amd/cs5536/Kconfig b/src/southbridge/amd/cs5536/Kconfig
index e7caf5e27a..18e3a2c853 100644
--- a/src/southbridge/amd/cs5536/Kconfig
+++ b/src/southbridge/amd/cs5536/Kconfig
@@ -19,12 +19,5 @@
config SOUTHBRIDGE_AMD_CS5536
bool
- select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-
-config UDELAY_TSC
- bool
- default y
- depends on SOUTHBRIDGE_AMD_CS5536
-
-
+ select UDELAY_TSC