diff options
author | Mike Loptien <mike.loptien@se-eng.com> | 2013-07-17 15:14:59 -0600 |
---|---|---|
committer | Bruce Griffith <Bruce.Griffith@se-eng.com> | 2013-08-15 18:40:11 +0200 |
commit | ac90d8013a26d99df21cb555bb313506ce32979c (patch) | |
tree | 3d5eedc01f54116d49a9aa649d081020d73c8097 /src/southbridge | |
parent | 81c70fb142326fe9e5ac5391cdd45f93c984e3e6 (diff) | |
download | coreboot-ac90d8013a26d99df21cb555bb313506ce32979c.tar.xz |
AMD Kabini: Split DSDT into common sections
Split the Family16 (Kabini) DSDT file into logical regions.
Olive Hill is the only mainboard and Kabini is the only NB/CPU
currently using Family16 AGESA code.
Change-Id: I9ef9a7245d14c59f664fc768d0ffa92ef5db7484
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3821
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge')
-rwxr-xr-x | src/southbridge/amd/agesa/hudson/acpi/audio.asl | 3 | ||||
-rwxr-xr-x | src/southbridge/amd/agesa/hudson/acpi/fch.asl | 118 | ||||
-rwxr-xr-x | src/southbridge/amd/agesa/hudson/acpi/lpc.asl | 37 | ||||
-rwxr-xr-x | src/southbridge/amd/agesa/hudson/acpi/pci_int.asl | 16 | ||||
-rwxr-xr-x | src/southbridge/amd/agesa/hudson/acpi/pcie.asl | 12 | ||||
-rwxr-xr-x | src/southbridge/amd/agesa/hudson/acpi/sleepstates.asl | 8 | ||||
-rwxr-xr-x | src/southbridge/amd/agesa/hudson/acpi/usb.asl | 14 |
7 files changed, 106 insertions, 102 deletions
diff --git a/src/southbridge/amd/agesa/hudson/acpi/audio.asl b/src/southbridge/amd/agesa/hudson/acpi/audio.asl index b9353e164e..3140215904 100755 --- a/src/southbridge/amd/agesa/hudson/acpi/audio.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/audio.asl @@ -19,7 +19,7 @@ * MA 02110-1301 USA */ -Device(AZHD) { +Device(AZHD) { /* 0:14.2 - HD Audio */ Name(_ADR, 0x00140002) OperationRegion(AZPD, PCI_Config, 0x00, 0x100) Field(AZPD, AnyAcc, NoLock, Preserve) { @@ -44,6 +44,7 @@ Device(AZHD) { offset (0x6C), MMDT, 16, } + Method (_INI, 0, NotSerialized) { If (LEqual (OSTP, 0x03)) diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index 573fa9ba5b..4fbf853038 100755 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -23,67 +23,54 @@ /* Describe the Southbridge devices */ -/* PCI slot 1, 2, 3 */ -Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } -} - -Device(SBUS) { - Name(_ADR, 0x00140000) -} /* end SBUS */ - -/* Primary (and only) IDE channel */ -Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" -} /* end IDEC */ - +/* 0:11.0 - SATA */ Device(STCR) { Name(_ADR, 0x00110000) #include "acpi/sata.asl" } /* end STCR */ +/* 0:14.0 - SMBUS */ +Device(SBUS) { + Name(_ADR, 0x00140000) +} /* end SBUS */ + #include "usb.asl" +/* 0:14.2 - HD Audio */ #include "audio.asl" +/* 0:14.3 - LPC */ #include "lpc.asl" -Device(HPBR) { +/* 0:14.7 - SD Controller */ +Device(SDCN) { + Name(_ADR, 0x00140007) +} /* end SDCN */ + +#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE +/* 0:14.1 - Primary (and only) IDE channel */ +Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" +} /* end IDEC */ + +/* 0:14.4 - PCI slot 1, 2, 3 */ +Device(PIBR) { Name(_ADR, 0x00140004) -} /* end HostPciBr */ + Name(_PRW, Package() {0x18, 4}) -Device(ACAD) { - Name(_ADR, 0x00140005) -} /* end Ac97audio */ + Method(_PRT, 0) { + Return (PCIB) + } +} +/* 0:14.6 - GEC Controller */ Device(ACMD) { Name(_ADR, 0x00140006) } /* end Ac97modem */ +#endif Name(CRES, ResourceTemplate() { - /* Set the Bus number and Secondary Bus number for the PCI0 device - * The Secondary bus range for PCI0 lets the system - * know what bus values are allowed on the downstream - * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which - * range from [0-0xFF] but they do not need to be - * sequential. - */ - - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x00FF, /* range maximum */ - 0x0000, /* translation */ - 0x0100, /* length */ - ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, @@ -94,12 +81,13 @@ Name(CRES, ResourceTemplate() { 0x0CF8 /* length */ ) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x03B0, /* range minimum */ - 0x03DF, /* range maximum */ - 0x0000, /* translation */ - 0x0030 /* length */ + 0x0000, /* address granularity */ + 0x03B0, /* range minimum */ + 0x03DF, /* range maximum */ + 0x0000, /* translation */ + 0x0030 /* length */ ) + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, /* address granularity */ 0x0D00, /* range minimum */ @@ -121,13 +109,13 @@ Method(_CRS, 0) { CreateDWordField(CRES, ^MMIO._LEN, MM1L) /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ Store(TOM1, MM1B) ShiftLeft(0x10000000, 4, Local0) Subtract(Local0, TOM1, Local0) @@ -137,13 +125,13 @@ Method(_CRS, 0) { } /* end of Method(_SB.PCI0._CRS) */ /* -* -* FIRST METHOD CALLED UPON BOOT -* -* 1. If debugging, print current OS and ACPI interpreter. -* 2. Get PCI Interrupt routing from ACPI VSM, this -* value is based on user choice in BIOS setup. -*/ + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ Method(_INI, 0) { /* DBGO("\\_SB\\_INI\n") */ /* DBGO(" DSDT.ASL code from ") */ @@ -161,11 +149,9 @@ Method(_INI, 0) { /* Determine the OS we're running on */ CkOT() - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ + /* TODO: It is unstable. */ + //#include "acpi/AmdImc.asl" /* Hudson IMC function */ + //ITZE() /* enable IMC Fan Control*/ } /* End Method(_SB._INI) */ Method(CkOT, 0){ diff --git a/src/southbridge/amd/agesa/hudson/acpi/lpc.asl b/src/southbridge/amd/agesa/hudson/acpi/lpc.asl index 1cd84f3e7e..3383ac8cdd 100755 --- a/src/southbridge/amd/agesa/hudson/acpi/lpc.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/lpc.asl @@ -17,37 +17,38 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* 0:14.3 - LPC */ Device(LIBR) { Name(_ADR, 0x00140003) /* Method(_INI) { * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") } */ /* End Method(_SB.SBRDG._INI) */ - OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space + OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space Field(CFG,DWordAcc,NoLock,Preserve){ Offset(0xA0), BAR,32} // SPI Controller Base Address Register (Index 0xA0) Device(LDRC) // LPC device: Resource consumption { - Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources - Name (CRS, ResourceTemplate () // Current Motherboard resources - { - Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address - 0x00000000, // Address Base - 0x00000000, // Address Length - BAR0 // Descriptor Name - ) - }) + Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources + Name (CRS, ResourceTemplate () // Current Motherboard resources + { + Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address + 0x00000000, // Address Base + 0x00000000, // Address Length + BAR0 // Descriptor Name + ) + }) - Method(_CRS,0,NotSerialized) - { - CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address - CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length - Store(BAR,SPIB) // SPI base address mapped - Store(0x1000,SPIL) // 4k space mapped - Return(CRS) - } + Method(_CRS,0,NotSerialized) + { + CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address + CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length + Store(BAR,SPIB) // SPI base address mapped + Store(0x1000,SPIL) // 4k space mapped + Return(CRS) + } } /* Real Time Clock Device */ diff --git a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl index 40c508ad45..384ed6128e 100755 --- a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl @@ -17,16 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - /* PCIe Configuration Space for 16 busses */ + /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */ Field(PCFG, ByteAcc, NoLock, Preserve) { /* Byte offsets are computed using the following technique: * ((bus number + 1) * ((device number * 8) * 4096)) + register offset * The 8 comes from 8 functions per device, and 4096 bytes per function config space */ - Offset(0x00088024), /* SATA reg 24h Bus 0, Device 17, Function 0 */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ STB5, 32, - Offset(0x00098042), /* OHCI0 reg 42h - Bus 0, Device 19, Function 0 */ + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ PT0D, 1, PT1D, 1, PT2D, 1, @@ -37,14 +37,14 @@ PT7D, 1, PT8D, 1, PT9D, 1, - Offset(0x000A0004), /* SMBUS reg 4h - Bus 0, Device 20, Function 0 */ + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ SBIE, 1, SBME, 1, - Offset(0x000A0008), /* SMBUS reg 8h - Bus 0, Device 20, Function 0 */ + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ SBRI, 8, - Offset(0x000A0014), /* SMBUS reg 14h - Bus 0, Device 20, Function 0 */ + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ SBB1, 32, - Offset(0x000A0078), /* SMBUS reg 78h - Bus 0, Device 20, Function 0 */ + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ ,14, P92E, 1, /* Port92 decode enable */ } @@ -181,6 +181,7 @@ if (Local0) { Decrement(Local0) } + Store(Local0, PIRA) } /* End Method(_SB.INTA._SRS) */ } /* End Device(INTA) */ @@ -467,5 +468,6 @@ if (Local0) { Decrement(Local0) } + Store(Local0, PIRH) } /* End Method(_SB.INTH._SRS) */ } /* End Device(INTH) */ diff --git a/src/southbridge/amd/agesa/hudson/acpi/pcie.asl b/src/southbridge/amd/agesa/hudson/acpi/pcie.asl index 742ebc8160..f130fb45d2 100755 --- a/src/southbridge/amd/agesa/hudson/acpi/pcie.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/pcie.asl @@ -46,13 +46,13 @@ /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, } /* GPM Port register */ diff --git a/src/southbridge/amd/agesa/hudson/acpi/sleepstates.asl b/src/southbridge/amd/agesa/hudson/acpi/sleepstates.asl index 7caeb4c5df..f8d0bb0855 100755 --- a/src/southbridge/amd/agesa/hudson/acpi/sleepstates.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/sleepstates.asl @@ -24,8 +24,8 @@ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ If (LAnd(SSFG, 0x01)) { Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ } -If (LAnd (SSFG, 0x02)) { - Name (_S2, Package () {0x02, 0x02, Zero, Zero} ) /* (S2) - "light" Suspend to RAM */ +If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ } If (LAnd(SSFG, 0x04)) { Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ @@ -36,5 +36,5 @@ If (LAnd(SSFG, 0x08)) { Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ -Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ -Name(CSMS, 0) /* Current System State */ +Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ +Name(CSMS, 0) /* Current System State */ diff --git a/src/southbridge/amd/agesa/hudson/acpi/usb.asl b/src/southbridge/amd/agesa/hudson/acpi/usb.asl index 2dbe124bca..fd0ba6419d 100755 --- a/src/southbridge/amd/agesa/hudson/acpi/usb.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/usb.asl @@ -19,46 +19,60 @@ * MA 02110-1301 USA */ +/* 0:12.0 - OHCI */ Device(UOH1) { Name(_ADR, 0x00120000) Name(_PRW, Package() {0x0B, 3}) } /* end UOH1 */ +/* 0:12.2 - EHCI */ Device(UOH2) { Name(_ADR, 0x00120002) Name(_PRW, Package() {0x0B, 3}) } /* end UOH2 */ +/* 0:13.0 - OHCI */ Device(UOH3) { Name(_ADR, 0x00130000) Name(_PRW, Package() {0x0B, 3}) } /* end UOH3 */ +/* 0:13.2 - EHCI */ Device(UOH4) { Name(_ADR, 0x00130002) Name(_PRW, Package() {0x0B, 3}) } /* end UOH4 */ +/* 0:16.0 - OHCI */ Device(UOH5) { Name(_ADR, 0x00160000) Name(_PRW, Package() {0x0B, 3}) } /* end UOH5 */ +/* 0:16.2 - EHCI */ Device(UOH6) { Name(_ADR, 0x00160002) Name(_PRW, Package() {0x0B, 3}) } /* end UOH5 */ +#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE +/* 0:14.5 - OHCI */ Device(UEH1) { Name(_ADR, 0x00140005) Name(_PRW, Package() {0x0B, 3}) } /* end UEH1 */ +#endif +/* 0:10.0 - XHCI 0*/ Device(XHC0) { Name(_ADR, 0x00100000) Name(_PRW, Package() {0x0B, 4}) } /* end XHC0 */ + +#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE +/* 0:10.1 - XHCI 1*/ Device(XHC1) { Name(_ADR, 0x00100001) Name(_PRW, Package() {0x0B, 4}) } /* end XHC1 */ +#endif |