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authorAntonello Dettori <dev@dettori.io>2016-09-03 10:45:33 +0200
committerMartin Roth <martinroth@google.com>2016-09-13 17:18:45 +0200
commitc6557d0807ddf616ceb84954639e39b840f2243a (patch)
treea67079d4f1f6a2fcbc60730e8ef7d1a176bd8f97 /src/southbridge
parentad62eddeb0de54654fe4ff42211cc74d519bd959 (diff)
downloadcoreboot-c6557d0807ddf616ceb84954639e39b840f2243a.tar.xz
southbridge/amd/sb600: transition away from device_t
Replace the use of the old device_t definition inside southbridge/amd/sb600. Change-Id: I0227cc0c611324f513f8170c9d8819a88af39b39 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16478 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/sb600/early_setup.c14
-rw-r--r--src/southbridge/amd/sb600/sb600.h4
2 files changed, 10 insertions, 8 deletions
diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c
index cbe8b0c881..2caa28bd79 100644
--- a/src/southbridge/amd/sb600/early_setup.c
+++ b/src/southbridge/amd/sb600/early_setup.c
@@ -36,7 +36,7 @@ static u8 pmio_read(u8 reg)
/* RPR 2.1: Get SB ASIC Revision. */
static u8 get_sb600_revision(void)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
if (dev == PCI_DEV_INVALID) {
@@ -63,7 +63,7 @@ static void sb600_lpc_init(void)
{
u8 reg8;
u32 reg32;
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */
/* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!!
@@ -102,7 +102,7 @@ static void sb600_lpc_init(void)
/* what is its usage? */
static u32 get_sbdn(u32 bus)
{
- device_t dev;
+ pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus);
@@ -192,7 +192,7 @@ void soft_reset(void)
void sb600_pci_port80(void)
{
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
/* P2P Bridge */
dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
@@ -237,7 +237,7 @@ void sb600_pci_port80(void)
void sb600_lpc_port80(void)
{
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
u32 reg32;
/* Enable LPC controller */
@@ -256,7 +256,7 @@ void sb600_lpc_port80(void)
/* sbDevicesPorInitTable */
static void sb600_devices_por_init(void)
{
- device_t dev;
+ pci_devfn_t dev;
u8 byte;
printk(BIOS_INFO, "sb600_devices_por_init()\n");
@@ -516,7 +516,7 @@ static void sb600_pmio_por_init(void)
*/
static void sb600_pci_cfg(void)
{
- device_t dev;
+ pci_devfn_t dev;
u8 byte;
/* SMBus Device, BDF:0-20-0 */
diff --git a/src/southbridge/amd/sb600/sb600.h b/src/southbridge/amd/sb600/sb600.h
index 5c1111adc4..94ee861536 100644
--- a/src/southbridge/amd/sb600/sb600.h
+++ b/src/southbridge/amd/sb600/sb600.h
@@ -34,9 +34,11 @@ extern void pm_iowrite(u8 reg, u8 value);
extern u8 pm_ioread(u8 reg);
extern void pm2_iowrite(u8 reg, u8 value);
extern u8 pm2_ioread(u8 reg);
-extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
+#ifndef __SIMPLE_DEVICE__
+extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
void sb600_enable(device_t dev);
+#endif
void sb600_lpc_port80(void);
void sb600_pci_port80(void);