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authorArthur Heymans <arthur@aheymans.xyz>2018-12-19 16:54:06 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-04-23 10:12:02 +0000
commitd893a2635fdd02e3fc12021aa4b0200a30d5a0de (patch)
treec0930430dfa687eb4ca7f0f6a92d6c6cdfce7150 /src/southbridge
parent63bc18e3285bf00d3239d89bc0c4cad97cbbc383 (diff)
downloadcoreboot-d893a2635fdd02e3fc12021aa4b0200a30d5a0de.tar.xz
sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock and enables console in general for the bootblock. Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30315 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/lynxpoint/Makefile.inc1
-rw-r--r--src/southbridge/intel/lynxpoint/bootblock.c3
-rw-r--r--src/southbridge/intel/lynxpoint/early_pch.c5
3 files changed, 4 insertions, 5 deletions
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index fd00f6c50e..04e0bc9909 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -46,6 +46,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c pch.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c
+bootblock-y += early_pch.c
romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c
romstage-y += early_spi.c rcba.c pmutil.c
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index 69fdd611d2..39e69257eb 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -79,4 +79,7 @@ void bootblock_early_southbridge_init(void)
/* Enable upper 128bytes of CMOS */
RCBA32(RC) = (1 << 2);
+
+ pch_enable_lpc();
+ mainboard_config_superio();
}
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index f615507dad..c36257747d 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -104,8 +104,6 @@ int early_pch_init(const void *gpio_map,
{
int wake_from_s3;
- pch_enable_lpc();
-
pch_enable_bars();
#if CONFIG(INTEL_LYNXPOINT_LP)
@@ -113,9 +111,6 @@ int early_pch_init(const void *gpio_map,
#else
setup_pch_gpios(gpio_map);
#endif
-
- mainboard_config_superio();
-
pch_generic_setup();
/* Enable SMBus for reading SPDs. */