summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
authorRonald G. Minnich <rminnich@gmail.com>2004-03-12 15:13:38 +0000
committerRonald G. Minnich <rminnich@gmail.com>2004-03-12 15:13:38 +0000
commite4fc0ab250bd88ad8833a90d9338fd5b35881ebc (patch)
tree7ac09324ee465b31f5bfb1ed6a479c301e0de53d /src/southbridge
parenta40a17c50cd10afea78bc5c1e41e486b9c4aa078 (diff)
downloadcoreboot-e4fc0ab250bd88ad8833a90d9338fd5b35881ebc.tar.xz
fixes for tyan
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/amd8131/amd8131_bridge.c12
-rw-r--r--src/southbridge/amd/amd8151/amd8151_agp3.c26
2 files changed, 24 insertions, 14 deletions
diff --git a/src/southbridge/amd/amd8131/amd8131_bridge.c b/src/southbridge/amd/amd8131/amd8131_bridge.c
index b96f46db45..44b04d8636 100644
--- a/src/southbridge/amd/amd8131/amd8131_bridge.c
+++ b/src/southbridge/amd/amd8131/amd8131_bridge.c
@@ -24,15 +24,15 @@ static void pcix_init(device_t dev)
/* Set drive strength */
word = pci_read_config16(dev, 0xe0);
- word = 0x0404;
+ word = 0x0808;
pci_write_config16(dev, 0xe0, word);
word = pci_read_config16(dev, 0xe4);
- word = 0x0404;
+ word = 0x0808;
pci_write_config16(dev, 0xe4, word);
/* Set impedance */
word = pci_read_config16(dev, 0xe8);
- word = 0x0404;
+ word = 0x0f0f;
pci_write_config16(dev, 0xe8, word);
/* Set discard unrequested prefetch data */
@@ -105,6 +105,12 @@ static void ioapic_enable(device_t dev)
value &= ~((1 << 1) | (1 << 0));
}
pci_write_config32(dev, 0x44, value);
+
+//BY LYH
+ value = pci_read_config32(dev, 0x4);
+ value |= 6;
+ pci_write_config32(dev, 0x4, value);
+//BY LYH END
}
static struct device_operations ioapic_ops = {
diff --git a/src/southbridge/amd/amd8151/amd8151_agp3.c b/src/southbridge/amd/amd8151/amd8151_agp3.c
index 2feeded66d..a4d4dce1a1 100644
--- a/src/southbridge/amd/amd8151/amd8151_agp3.c
+++ b/src/southbridge/amd/amd8151/amd8151_agp3.c
@@ -11,12 +11,16 @@
static void agp3bridge_init(device_t dev)
{
- uint32_t dword;
+ uint8_t byte;
+
+ byte = pci_read_config32(dev, 0x04);
+ byte |= 0x07;
+ pci_write_config8(dev, 0x04, byte);
+
+ byte = pci_read_config32(dev, 0xce);
+ byte |= 3<<2;
+ pci_write_config8(dev, 0xce, byte);
- dword = pci_read_config8(dev, 0x04);
- dword |= 0x07;
- pci_write_config8(dev, 0x04, dword);
-
return;
}
@@ -31,7 +35,7 @@ static struct device_operations agp3bridge_ops = {
static struct pci_driver agp3bridge_driver __pci_driver = {
.ops = &agp3bridge_ops,
.vendor = PCI_VENDOR_ID_AMD,
- .device = 0x7455,
+ .device = 0x7455, // AGP Bridge
};
@@ -41,19 +45,19 @@ static void agp3dev_enable(device_t dev)
// AGP enable
value = pci_read_config32(dev, 0xa8);
- value |= (1<<8);
+ value |= (3<<8)|2; //AGP 8x
pci_write_config32(dev, 0xa8, value);
-
+/*
// linkA 8bit-->16bit
value = pci_read_config32(dev, 0xc4);
- value |= (11<<24);
+ value |= (0x11<<24);
pci_write_config32(dev, 0xc4, value);
// linkA 200-->600
value = pci_read_config32(dev, 0xcc);
value |= (4<<8);
pci_write_config32(dev, 0xcc, value);
-
+*/
value = pci_read_config32(dev, 0x4);
value |= 6;
@@ -72,6 +76,6 @@ static struct device_operations agp3dev_ops = {
static struct pci_driver agp3dev_driver __pci_driver = {
.ops = &agp3dev_ops,
.vendor = PCI_VENDOR_ID_AMD,
- .device = 0x7454,
+ .device = 0x7454, //AGP Device
};