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| author | Simon Glass <sjg@chromium.org> | 2018-07-12 15:26:07 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-16 07:41:14 +0000 |
| commit | 46255f7ee4728e0ee02c0cb8d9edeeee1a8e5361 (patch) | |
| tree | 61f626813cc3f3f9f4400b7c00bbcaef552faf68 /src/southbridge | |
| parent | 457253cdc6cac0eeef47c2dd4fbd2f93e1d34ef2 (diff) | |
| download | coreboot-46255f7ee4728e0ee02c0cb8d9edeeee1a8e5361.tar.xz | |
Kconfig: Make the EM100 config option common
This applied to AMD devices as well as Intel, although the mechanism is
different. Move the option to a common place.
BUG=b:111363976
TEST=USE=em100-mode emerge-reef coreboot
See that a message appears:
* Enabling em100 mode (slow SPI flash)
Change-Id: Iea437bdf42e7bc49b1d28c812bfc6128e3eb68bd
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/27467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/common/firmware/Kconfig | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 30c9aaf262..c9cf6f8760 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -26,6 +26,7 @@ comment "Intel Firmware" config HAVE_IFD_BIN bool "Add Intel descriptor.bin file" + select HAVE_EM100_SUPPORT # We use ifdtool to enable this. help The descriptor binary @@ -34,12 +35,6 @@ config IFD_BIN_PATH default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD -config EM100 - bool "Configure IFD for EM100 usage" - depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD - help - Set SPI frequency to 20MHz and disable Dual Output Fast Read Support - config HAVE_ME_BIN bool "Add Intel ME/TXE firmware" depends on HAVE_IFD_BIN |