diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-27 11:27:56 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-29 07:32:43 +0200 |
| commit | 65e8f647bc55ee28bd389789788e666279537510 (patch) | |
| tree | e93254e6c05cebec7beaf698437bb576aae656b6 /src/southbridge | |
| parent | 7b3512dde3efa3d25d715bb61326ebfc995e9a69 (diff) | |
| download | coreboot-65e8f647bc55ee28bd389789788e666279537510.tar.xz | |
intel romstage: Use run_ramstage()
Change-Id: I22a33e6027a4e807f7157a0dfafbd6377bc1285d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15461
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/fsp_i89xx/romstage.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/romstage.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c index f14dd5b7f8..5bcc8fa794 100644 --- a/src/southbridge/intel/fsp_i89xx/romstage.c +++ b/src/southbridge/intel/fsp_i89xx/romstage.c @@ -21,7 +21,6 @@ #include <timestamp.h> #include <arch/cpu.h> #include <arch/io.h> -#include <arch/stages.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> @@ -31,6 +30,7 @@ #include <console/console.h> #include <console/usb.h> #include <halt.h> +#include <program_loading.h> #include <reset.h> #include <drivers/intel/fsp1_0/fsp_util.h> #include <northbridge/intel/fsp_sandybridge/northbridge.h> @@ -214,7 +214,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { timestamp_add_now(TS_END_ROMSTAGE); - copy_and_run(); + run_ramstage(); } uint64_t get_initial_timestamp(void) diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 2fe7b2e31e..042aaf93dd 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -26,12 +26,12 @@ #include <cbmem.h> #include <console/console.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <program_loading.h> #include "northbridge/intel/fsp_rangeley/northbridge.h" #include "southbridge/intel/fsp_rangeley/soc.h" #include "southbridge/intel/fsp_rangeley/gpio.h" #include "southbridge/intel/fsp_rangeley/romstage.h" #include <arch/cpu.h> -#include <arch/stages.h> #include <cpu/x86/msr.h> #include "gpio.h" @@ -129,7 +129,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { post_code(0x4f); /* Load the ramstage. */ - copy_and_run(); + run_ramstage(); while (1); } |