diff options
| author | Nico Huber <nico.h@gmx.de> | 2019-11-17 02:34:53 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-18 11:51:57 +0000 |
| commit | 6760e0bdcd37e904c121800652cd2ac3920d9cd9 (patch) | |
| tree | 576cc3efed90173d7093f4f93878a42d0bbe363f /src/southbridge | |
| parent | 1d29b7bbceed82a2161e249474086169ac3039f4 (diff) | |
| download | coreboot-6760e0bdcd37e904c121800652cd2ac3920d9cd9.tar.xz | |
sb/intel/bd82x6x: Handle enabling of GbE
The integrated GbE port is toggled via the Backed-Up Control (BUC)
register. We already disable it according to the devicetree setting
but never enabled it. This could lead to the confusing situation
that it was disabled before (different build, vendor BIOS, etc.)
but shouldn't be anymore.
As we need a full reset after enabling GbE, do it in early PCH init.
Change-Id: I9db3d1923684b938d2c9f5b369b0953570c7fc15
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_pch.c | 28 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.c | 2 |
2 files changed, 28 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 8ffb22e140..b12ad38f47 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -16,6 +16,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <arch/cbfs.h> +#include <cf9_reset.h> #include <ip_checksum.h> #include <device/pci_def.h> #include <southbridge/intel/common/gpio.h> @@ -253,6 +254,30 @@ static void pch_generic_setup(void) write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ } +static void pch_enable_gbe(void) +{ + uint8_t wanted_buc; + + /* Don't do this in the bootblock, it might be RO. So one + couldn't change the setting later in an updated romstage. */ + if (ENV_BOOTBLOCK) + return; + + const struct device *const gbe = pcidev_on_root(0x19, 0); + if (gbe && gbe->enabled) + wanted_buc = RCBA8(BUC) & ~PCH_DISABLE_GBE; + else + wanted_buc = RCBA8(BUC) | PCH_DISABLE_GBE; + + if (RCBA8(BUC) != wanted_buc) { + RCBA8(BUC) = wanted_buc; + /* Be double sure not to reset for naught. */ + if (RCBA8(BUC) != wanted_buc) + return; + full_reset(); + } +} + static void pch_enable_lpc_decode(void) { /* @@ -292,7 +317,6 @@ __weak void mainboard_pch_lpc_setup(void) void early_pch_init(void) { - pch_enable_lpc_decode(); mainboard_pch_lpc_setup(); @@ -301,5 +325,7 @@ void early_pch_init(void) pch_generic_setup(); + pch_enable_gbe(); + setup_pch_gpios(&mainboard_gpio_map); } diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 3cd39a6706..5c2b130b7e 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -166,7 +166,7 @@ static void pch_hide_devfn(unsigned int devfn) RCBA32_OR(FD2, PCH_DISABLE_KT); break; case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ - RCBA32_OR(BUC, PCH_DISABLE_GBE); + /* BUC is already handled in `early_pch.c`. */ break; case PCI_DEVFN(26, 0): /* EHCI #2 */ RCBA32_OR(FD, PCH_DISABLE_EHCI2); |