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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-06-05 07:19:31 +0300 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-06-12 05:19:39 +0200 |
| commit | 8351243e4a99c7159ec3257db272b735efff218c (patch) | |
| tree | 7f71f21f953707cd732aa9201af40c194b0f7fba /src/southbridge | |
| parent | 083d35551c5cce5c26e5bc19f400878727594869 (diff) | |
| download | coreboot-8351243e4a99c7159ec3257db272b735efff218c.tar.xz | |
Fix i82801a/b/c/d IOAPIC
Setting IRQ delivery to FSB got lost in the rebase process
for commit e6143531.
I captured following error on dmesg and this patch fixes it for
i82801dx.
..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
..MP-BIOS bug: 8254 timer not connected to IO-APIC
...trying to set up timer (IRQ0) through the 8259A ...
..... (found apic 0 pin 2) ...
....... failed.
...trying to set up timer as Virtual Wire IRQ...
..... works.
Change-Id: I0768976cc6b0deab213ad9bd4771e0f278de634c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3371
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/i82801ax/lpc.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801bx/lpc.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801cx/lpc.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801dx/lpc.c | 6 |
4 files changed, 24 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index db03a5897c..212c95f270 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -104,6 +104,12 @@ static void i82801ax_enable_ioapic(struct device *dev) printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); set_ioapic_id(IO_APIC_ADDR, 0x02); + + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write(IO_APIC_ADDR, 0x03, 0x01); } static void i82801ax_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index c5e976c136..13b15996dc 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -105,6 +105,12 @@ static void i82801bx_enable_ioapic(struct device *dev) printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); set_ioapic_id(IO_APIC_ADDR, 0x02); + + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write(IO_APIC_ADDR, 0x03, 0x01); } static void i82801bx_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index 79998bc722..f9c0ece4fe 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -42,6 +42,12 @@ static void i82801cx_enable_ioapic(struct device *dev) printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); set_ioapic_id(IO_APIC_ADDR, 0x02); + + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write(IO_APIC_ADDR, 0x03, 0x01); } // This is how interrupts are received from the Super I/O chip diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 69ec110d6e..cf4e132e3b 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -68,6 +68,12 @@ static void i82801dx_enable_ioapic(struct device *dev) printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); set_ioapic_id(IO_APIC_ADDR, 0x02); + + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write(IO_APIC_ADDR, 0x03, 0x01); } static void i82801dx_enable_serial_irqs(struct device *dev) |