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| author | Li-Ta Lo <ollie@lanl.gov> | 2004-09-07 19:24:40 +0000 |
|---|---|---|
| committer | Li-Ta Lo <ollie@lanl.gov> | 2004-09-07 19:24:40 +0000 |
| commit | 981faa09e4b7edf498b1b1f353cc100541abb859 (patch) | |
| tree | 3080946ad8619ff6075f477a1237a5d5a1343030 /src/southbridge | |
| parent | 43dd85e7ec30f53364c7ac5abc84d55b104ae00f (diff) | |
| download | coreboot-981faa09e4b7edf498b1b1f353cc100541abb859.tar.xz | |
rename variable from addr to dev
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_enable_rom.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111_enable_rom.c b/src/southbridge/amd/amd8111/amd8111_enable_rom.c index 425108dc9a..468801a6c4 100644 --- a/src/southbridge/amd/amd8111/amd8111_enable_rom.c +++ b/src/southbridge/amd/amd8111/amd8111_enable_rom.c @@ -2,14 +2,14 @@ static void amd8111_enable_rom(void) { unsigned char byte; - device_t addr; + device_t dev; /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */ /* Locate the amd8111 */ - addr = pci_locate_device(PCI_ID(0x1022, 0x7468), 0); + dev = pci_locate_device(PCI_ID(0x1022, 0x7468), 0); /* Set the 4MB enable bit bit */ - byte = pci_read_config8(addr, 0x43); + byte = pci_read_config8(dev, 0x43); byte |= 0x80; - pci_write_config8(addr, 0x43, byte); + pci_write_config8(dev, 0x43, byte); } |