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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-04-10 15:52:47 -0500 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-04-11 23:25:04 +0200 |
| commit | d1b6ff80c017e671c1e2229ee0d659e491ab53f5 (patch) | |
| tree | 7e5ef7b603cddab8ad7b2c84fbbd25c6410ccae5 /src/southbridge | |
| parent | 796e77ef2529507efdbb671fdfb3e79f9ed0ed18 (diff) | |
| download | coreboot-d1b6ff80c017e671c1e2229ee0d659e491ab53f5.tar.xz | |
sb/amd/sp5100: Enable CPU reset timing option per RPR v3.02
Change-Id: Ifb568ca126283e533232f52175d6147ee500220c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14307
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/sb700/early_setup.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 26ee8366ce..aae845fbf2 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -677,6 +677,11 @@ static void sb700_pmio_por_init(void) pmio_write(0xbb, byte); #if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 + /* RPR 2.26 Alter CPU reset timing */ + byte = pmio_read(0xb2); + byte |= 0x1 << 2; /* Enable CPU reset timing option */ + pmio_write(0xb2, byte); + /* Work around system clock drift issues */ byte = pmio_read(0xd4); byte |= 0x1 << 6; /* Enable alternate 14MHz clock source */ |