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| author | Li-Ta Lo <ollie@lanl.gov> | 2004-03-23 21:28:05 +0000 |
|---|---|---|
| committer | Li-Ta Lo <ollie@lanl.gov> | 2004-03-23 21:28:05 +0000 |
| commit | e52666931a3e34895b3f3b92641de9774ab722ec (patch) | |
| tree | 890bb66a0a16ec7a57230283f000ee91eeb0b384 /src/southbridge | |
| parent | 9f46132e9627d24f3ad76619cf3340006a4012fb (diff) | |
| download | coreboot-e52666931a3e34895b3f3b92641de9774ab722ec.tar.xz | |
Doxidization, reformat
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c index d3fdf3b7ba..ccf26b623e 100644 --- a/src/southbridge/amd/amd8111/amd8111.c +++ b/src/southbridge/amd/amd8111/amd8111.c @@ -15,7 +15,7 @@ void amd8111_enable(device_t dev) /* See if we are on the behind the amd8111 pci bridge */ bus_dev = dev->bus->dev; if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) && - (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) { + (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) { unsigned devfn; devfn = bus_dev->path.u.pci.devfn + (1 << 3); lpc_dev = dev_find_slot(bus_dev->bus->secondary, devfn); @@ -26,11 +26,12 @@ void amd8111_enable(device_t dev) lpc_dev = dev_find_slot(dev->bus->secondary, devfn); index = dev->path.u.pci.devfn & 7; } + if ((!lpc_dev) || (index >= 16)) { return; } if ((lpc_dev->vendor != PCI_VENDOR_ID_AMD) || - (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) { + (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) { uint32_t id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); if (id != (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8111_ISA << 16))) { @@ -48,6 +49,6 @@ void amd8111_enable(device_t dev) } struct chip_control southbridge_amd_amd8111_control = { - .name = "AMD 8111", + .name = "AMD 8111 Southbridge", .enable_dev = amd8111_enable, }; |